1# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
2# an affiliate of Cypress Semiconductor Corporation
3#
4# SPDX-License-Identifier: Apache-2.0
5
6description: |
7  Infineon CAT1 Pinctrl container node
8
9  This is a singleton node responsible for controlling the pin function selection
10  and pin properties. For example, you can use this node to route
11  UART0 RX to a particular port/pin and enable the pull-up resistor on that
12  pin.
13
14  The node has the 'pinctrl' node label set in SoC's devicetree,
15  so you can modify it like this:
16
17  &pinctrl {
18      /* Your modifications go here */
19  };
20
21  Pin configuration can also specify the pin properties, for example the
22  'bias-pull-up' property. Here is a list of the supported standard pin
23  properties:
24    * bias-high-impedance
25    * bias-pull-up
26    * bias-pull-down
27    * drive-open-drain
28    * drive-open-source
29    * drive-push-pull   (strong)
30    * input-enable      (input-buffer)
31
32  Infineon CAT1 SoC's devicetree includes a set of pre-defined pin control
33  Nodes, which can be found via MPN dtsi.
34  For example, board cy8cproto_062_4343w uses the CY8C624ABZI_S2D44 part, so
35  board dts (boards\arm\cy8cproto_062_4343w\cy8cproto_062_4343w.dts) includes MPN dts
36  (infineon/psoc6/mpns/CY8C624ABZI_S2D44.dtsi).
37
38  Each MPN dtsi includes package dtsi (../psoc6_xx/psoc6_xx.yyy-zzz.dtsi),
39  For example, CY8C624ABZI_S2D44 includes "../psoc6_02/psoc6_02.124-bga.dtsi".
40
41  An example of pre-defined pin control from package dtsi (e.g. psoc6_02.124-bga.dtsi):
42  p3_0_scb2_uart_rx - RX pin UART2 (SCB2) which connected to port3.0
43
44    /omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
45          pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
46    };
47
48  Refer to psoc6_02.124-bga.dtsi for the list of all pre-defined pin control nodes.
49
50  NOTE1 Pre-defined pin control nodes use macro DT_CAT1_PINMUX to
51    initialize pinmux. DT_CAT1_PINMUX has the following input parameters
52    DT_CAT1_PINMUX(port_number, pin_number, hsiom),
53    hsiom is defined in the HSIOM_SEL_xxx macros in the
54    zephyr\include\zephyr\dt-bindings\pinctrl\ifx_cat1-pinctrl.h file.
55
56        You can use DT_CAT1_PINMUX to define your own pin control node:
57          &pinctrl {
58              my_uart_rx: my_uart_rx {
59                  pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
60              };
61          };
62
63  NOTE2 Pre-defined pin control nodes do not have bias pin configuration.
64    The bias configuration can be updated in board-pinctrl.dtsi
65    &pinctrl {
66      /* Configure pin control Bias mode for uart2 pins */
67      p3_1_scb2_uart_tx {
68        drive-push-pull;
69      };
70
71      p3_0_scb2_uart_rx {
72        input-enable;
73      };
74
75      p3_2_scb2_uart_rts {
76        drive-push-pull;
77      };
78
79      p3_3_scb2_uart_cts {
80        input-enable;
81      };
82    };
83
84  An example of the usage of pre-defined pin control nodes in your board's DTS file:
85
86    &uart5 {
87      pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;
88      pinctrl-names = "default";
89    };
90
91    /* Configure pin control bias mode for uart5 pins */
92    &p5_1_scb5_uart_tx {
93      drive-push-pull;
94    };
95
96    &p5_0_scb5_uart_rx {
97      input-enable;
98    };
99
100compatible: "infineon,cat1-pinctrl"
101
102include: base.yaml
103
104child-binding:
105  description: This binding gives a base representation of the Infineon CAT1 pins configuration
106  include:
107    - name: pincfg-node.yaml
108      property-allowlist:
109        - bias-high-impedance
110        - bias-pull-down
111        - bias-pull-up
112        - drive-push-pull
113        - drive-open-drain
114        - drive-open-source
115        - input-enable
116
117  properties:
118    pinmux:
119      description: |
120        Encodes port/pin and alternate function.
121      required: true
122      type: int
123