1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_PS2_H 8 #define _MEC_PS2_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* 14 * PS2 TRX Buffer register 15 * Writes -> Transmit buffer 16 * Read <- Receive buffer 17 */ 18 #define MCHP_PS2_TRX_BUFF_REG_MASK 0xffu 19 20 /* PS2 Control register */ 21 #define MCHP_PS2_CTRL_REG_MASK 0x3fu 22 23 /* Select Transmit or Receive */ 24 #define MCHP_PS2_CTRL_TR_POS 0u 25 #define MCHP_PS2_CTRL_TR_RX 0u 26 #define MCHP_PS2_CTRL_TR_TX BIT(MCHP_PS2_CTRL_TR_POS) 27 28 /* Enable PS2 state machine */ 29 #define MCHP_PS2_CTRL_EN_POS 1u 30 #define MCHP_PS2_CTRL_EN BIT(MCHP_PS2_CTRL_EN_POS) 31 32 /* Protocol parity selection */ 33 #define MCHP_PS2_CTRL_PAR_POS 2u 34 #define MCHP_PS2_CTRL_PAR_MASK0 0x03u 35 #define MCHP_PS2_CTRL_PAR_MASK 0x0cu 36 #define MCHP_PS2_CTRL_PAR_ODD 0u 37 #define MCHP_PS2_CTRL_PAR_EVEN 0x04u 38 #define MCHP_PS2_CTRL_PAR_IGNORE 0x08u 39 #define MCHP_PS2_CTRL_PAR_RSVD 0x0cu 40 41 /* Protocol stop bit selection */ 42 #define MCHP_PS2_CTRL_STOP_POS 4u 43 #define MCHP_PS2_CTRL_STOP_MASK0 0x03u 44 #define MCHP_PS2_CTRL_STOP_MASK 0x30u 45 #define MCHP_PS2_CTRL_STOP_ACT_HI 0u 46 #define MCHP_PS2_CTRL_STOP_ACT_LO 0x10u 47 #define MCHP_PS2_CTRL_STOP_IGNORE 0x20u 48 #define MCHP_PS2_CTRL_STOP_RSVD 0x30u 49 50 /* PS2 Status register */ 51 #define MCHP_PS2_STATUS_REG_MASK 0xffu 52 #define MCHP_PS2_STATUS_RW1C_MASK 0xaeu 53 #define MCHP_PS2_STATUS_RO_MASK 0x51u 54 /* RX Data Ready(Read-Only) */ 55 #define MCHP_PS2_STATUS_RXD_RDY_POS 0 56 #define MCHP_PS2_STATUS_RXD_RDY BIT(MCHP_PS2_STATUS_RXD_RDY_POS) 57 /* RX Timeout(R/W1C) */ 58 #define MCHP_PS2_STATUS_RX_TMOUT_POS 1 59 #define MCHP_PS2_STATUS_RX_TMOUT BIT(MCHP_PS2_STATUS_RX_TMOUT_POS) 60 /* Parity Error(R/W1C) */ 61 #define MCHP_PS2_STATUS_PE_POS 2 62 #define MCHP_PS2_STATUS_PE BIT(MCHP_PS2_STATUS_PE_POS) 63 /* Framing Error(R/W1C) */ 64 #define MCHP_PS2_STATUS_FE_POS 3 65 #define MCHP_PS2_STATUS_FE BIT(MCHP_PS2_STATUS_FE_POS) 66 /* Transmitter is Idle(Read-Only) */ 67 #define MCHP_PS2_STATUS_TX_IDLE_POS 4 68 #define MCHP_PS2_STATUS_TX_IDLE BIT(MCHP_PS2_STATUS_TX_IDLE_POS) 69 /* Transmitter timeout(R/W1C) */ 70 #define MCHP_PS2_STATUS_TX_TMOUT_POS 5 71 #define MCHP_PS2_STATUS_TX_TMOUT BIT(MCHP_PS2_STATUS_TX_TMOUT_POS) 72 /* RX is Busy(Read-Only) */ 73 #define MCHP_PS2_STATUS_RX_BUSY_POS 6 74 #define MCHP_PS2_STATUS_RX_BUSY BIT(MCHP_PS2_STATUS_RX_BUSY_POS) 75 /* Transmitter start timeout(R/W1C) */ 76 #define MCHP_PS2_STATUS_TX_ST_TMOUT_POS 7 77 #define MCHP_PS2_STATUS_TX_ST_TMOUT BIT(MCHP_PS2_STATUS_TX_ST_TMOUT_POS) 78 79 /* PS2 Protocol bit positions */ 80 #define MCHP_PS2_PROT_START_BIT_POS 1 81 #define MCHP_PS2_PROT_DATA_BIT0_POS 2 82 #define MCHP_PS2_PROT_DATA_BIT1_POS 3 83 #define MCHP_PS2_PROT_DATA_BIT2_POS 4 84 #define MCHP_PS2_PROT_DATA_BIT3_POS 5 85 #define MCHP_PS2_PROT_DATA_BIT4_POS 6 86 #define MCHP_PS2_PROT_DATA_BIT5_POS 7 87 #define MCHP_PS2_PROT_DATA_BIT6_POS 8 88 #define MCHP_PS2_PROT_DATA_BIT7_POS 9 89 #define MCHP_PS2_PROT_PARITY_POS 10 90 #define MCHP_PS2_PROT_STOP_BIT_POS 11 91 92 /** @brief PS/2 controller */ 93 struct ps2_regs { 94 volatile uint32_t TRX_BUFF; 95 volatile uint32_t CTRL; 96 volatile uint32_t STATUS; 97 }; 98 99 #endif /* #ifndef _MEC_PS2_H */ 100
