Lines Matching +full:control +full:- +full:selection

4  * SPDX-License-Identifier: Apache-2.0
7 /* Port 0~4 PHY Control Register. */
23 /* Link speed selection offset. */
44 /* Address Table Control And Status Register PHY Address */
46 /* Address Table Control And Status Register Register SAddress */
101 /* WoL Control Register PHY Address */
103 /* WoL Control Register Register Address */
114 /* Interrupt Mask & Control Register PHY Address. */
116 /* Interrupt Mask & Control Register Register Address. */
120 /* Port 5 Force Speed control bit */
122 /* Port 5 Force Duplex control bit */
124 /* Port 5 Force Link control bit. Only available in force mode. */
126 /* Port 5 Force Mode Enable control bit. Only available for
131 /* Port 5 50MHz Clock Output Enable control bit. Only available when Port 5
135 /* Port 5 Clock Source Selection control bit. Only available when Port 5
141 /* IRQ and LED Control Register. */
145  * 100M link fail                       - LED off
146  * 100M link ok and no TX/RX activity   - LED on
147  * 100M link ok and TX/RX activity      - LED blinking
149  * No colision:                         - LED off
150  * Colision:                            - LED blinking
152  * 10M link fail                        - LED off
153  * 10M link ok and no TX/RX activity    - LED on
154  * 10M link ok and TX/RX activity       - LED blinking