1# Copyright 2022, 2024 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  MCI IO MUX pin control node. This node defines pin configurations in pin
6  groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
7  group within the pin configuration defines a peripheral's pin configuration.
8  Each numbered subgroup represents pins with shared configuration for that
9  peripheral. The 'pinmux' property of each group selects the pins to be
10  configured with these properties. For example, here is a configuration
11  for FLEXCOMM0 pins:
12
13  pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
14    group0 {
15      pinmux = <IO_MUX_FC0_USART_DATA_IO2>,
16              <IO_MUX_FC0_USART_DATA_IO3>;
17      slew-rate = "normal";
18    };
19  };
20
21  If only the required properties are supplied, the pin will be configured
22  as normal drive strength and no pull. This corresponds to the following
23  pin settings:
24  PAD_PU_PD_ENx = (0x0 << pin_index)
25  SR_CONFIGx = (0x2 << pin_index)
26
27  Note
28
29  Note the inherited pinctrl properties defined below have the following effects:
30  bias-pull-up: PAD_PU_PD_ENx= (0x1 << pin_index)
31  bias-pull-down: PAD_PU_PD_ENx= (0x10 << pin_index)
32
33compatible: "nxp,mci-io-mux"
34
35include:
36  - name: base.yaml
37
38child-binding:
39  description: MCI IO MUX pin controller pin group
40  child-binding:
41    description: |
42      MCI IO MUX pin controller pin configuration node
43    include:
44      - name: pincfg-node.yaml
45        property-allowlist:
46          - bias-pull-up
47          - bias-pull-down
48    properties:
49      pinmux:
50        required: true
51        type: array
52        description: |
53          Pin mux selection for this group. See the SOC level pinctrl header
54          file in NXP's HAL for a defined list of these options.
55      slew-rate:
56        required: true
57        type: string
58        enum:
59          - "slow"
60          - "normal"
61          - "fast"
62          - "ultra"
63        description: |
64          Pin output slew rate. Sets the GPIOxx_SR field in the SR_CONFIGx
65          register.
66          0 - slow slew rate
67          1 - normal slew rate
68          2 - fast slew rate
69          3 - fastest slew rate (ultra)
70