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Searched +full:clk +full:- +full:out +full:- +full:div (Results 1 – 16 of 16) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Drenesas,ra-cgc-busclk.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-cgc-busclk"
8 include: [clock-controller.yaml, base.yaml]
11 clk-out-div:
14 - 0
15 - 1
16 - 2
19 - 0: disable
20 - 1: EBCLK div/1
21 - 2: EBCLK div/2
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/Zephyr-latest/drivers/clock_control/
Dclock_control_rpi_pico.c2 * Copyright (c) 2022 Andrei-Edward Popa
5 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
16 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
57 #define CLK_SRC_IS(clk, src) \ argument
58 DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
68 * Using the 'clock-names[0]' for expanding macro to frequency value.
69 * The 'clock-names[0]' is set same as label value that given to the node itself.
72 #define CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, clk) argument
73 #define SRC_CLOCK(clk) DT_STRING_TOKEN_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), \ argument
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Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
251 timeout = ldev->timeout.lock; in litex_clk_wait()
253 timeout = ldev->timeout.drdy; in litex_clk_wait()
257 timeout--; in litex_clk_wait()
262 return -ETIME; in litex_clk_wait()
303 ldev->g_config.mul = 1; in litex_clk_update_global_config()
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/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2040.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
13 #include <zephyr/dt-bindings/reset/rp2040_reset.h>
28 die-temp0 = &die_temp;
32 #address-cells = <1>;
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/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
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Dr7fa8t1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc {
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(24)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
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Dr7fa8d1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 sdram: sdram-controller@40002000 {
13 compatible = "renesas,ra-sdram";
14 #address-cells = <1>;
15 #size-cells = <0>;
20 lcdif: display-controller@40342000 {
21 compatible = "renesas,ra-glcdc";
25 interrupt-names = "line";
30 compatible = "renesas,ra-mipi-dsi";
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/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6m1ad3cfp.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
13 compatible = "mmio-sram";
17 flash-controller@407e0000 {
19 #address-cells = <1>;
20 #size-cells = <1>;
23 compatible = "soc-nv-flash";
29 compatible = "renesas,ra-sce7-rng";
34 channel-count = <11>;
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Dr7fa6m2ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-sci";
21 interrupt-names = "rxi", "txi", "tei", "eri";
26 compatible = "renesas,ra-sci-uart";
33 compatible = "renesas,ra-sci";
35 interrupt-names = "rxi", "txi", "tei", "eri";
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Dr7fa6m3ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-gpio-ioport";
22 gpio-controller;
23 #gpio-cells = <2>;
29 compatible = "renesas,ra-gpio-ioport";
32 gpio-controller;
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Dr7fa6m4ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-sci";
21 interrupt-names = "rxi", "txi", "tei", "eri";
26 compatible = "renesas,ra-sci-uart";
33 compatible = "renesas,ra-sci";
35 interrupt-names = "rxi", "txi", "tei", "eri";
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Dr7fa6m5xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-gpio-ioport";
22 gpio-controller;
23 #gpio-cells = <2>;
29 compatible = "renesas,ra-gpio-ioport";
32 gpio-controller;
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/Zephyr-latest/drivers/sdhc/
Dsdhc_esp32.c4 * SPDX-License-Identifier: Apache-2.0
81 uint32_t bus_clock; /* Value in Hz. ESP-IDF functions use kHz instead */
98 * - one is the clock generator which drives SDMMC peripheral,
99 * it can be configured using sdio_hw->clock register. It can generate
101 * - 4 clock dividers inside SDMMC peripheral, which can divide clock
105 * For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
107 * Note: for non-UHS-1 cards, HS mode is optional.
121 static int sdmmc_host_set_clk_div(sdmmc_dev_t *sdio_hw, int div) in sdmmc_host_set_clk_div() argument
123 if (!((div > 1) && (div <= 16))) { in sdmmc_host_set_clk_div()
124 LOG_ERR("Invalid parameter 'div'"); in sdmmc_host_set_clk_div()
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/Zephyr-latest/boards/telink/tlsr9518adk80d/doc/
Dindex.rst17 The TLSR9518A SoC integrates a powerful 32-bit RISC-V MCU, DSP, AI Engine, 2.4 GHz ISM Radio, 256
28 - RF conducted antenna
29 - 1 MB External Flash memory with reset button
30 - Chip reset button
31 - Mini USB interface
32 - 4-wire JTAG
33 - 4 LEDs, Key matrix up to 4 keys
34 - 2 line-in function (Dual Analog microphone supported when switching jumper from microphone path)
35 - Dual Digital microphone
36 - Stereo line-out
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/Zephyr-latest/drivers/spi/
Dspi_ll_stm32.c4 * SPDX-License-Identifier: Apache-2.0
35 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
39 #include <zephyr/linker/linker-defs.h>
79 struct spi_stm32_data *data = dev->data; in spi_stm32_pm_policy_state_lock_get()
81 if (!data->pm_policy_state_on) { in spi_stm32_pm_policy_state_lock_get()
82 data->pm_policy_state_on = true; in spi_stm32_pm_policy_state_lock_get()
95 struct spi_stm32_data *data = dev->data; in spi_stm32_pm_policy_state_lock_put()
97 if (data->pm_policy_state_on) { in spi_stm32_pm_policy_state_lock_put()
98 data->pm_policy_state_on = false; in spi_stm32_pm_policy_state_lock_put()
119 * the linker to avoid potential DMA cache-coherency problems.
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
95 allow distinguishing between an out of range bitrate/sample point, an unsupported bitrate, and a
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
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