Lines Matching +full:clk +full:- +full:out +full:- +full:div

2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-cgc-busclk"
8 include: [clock-controller.yaml, base.yaml]
11   clk-out-div:
14     - 0
15     - 1
16     - 2
19       - 0: disable
20       - 1: EBCLK div/1
21       - 2: EBCLK div/2
26     - 0
27     - 1
30       - 0: disable
31       - 1: enable