1 /*
2 * Copyright (c) 2022 Andrei-Edward Popa
3 * Copyright (c) 2023 TOKITA Hiroshi
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT raspberrypi_pico_clock_controller
9
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/drivers/reset.h>
13 #if defined(CONFIG_SOC_SERIES_RP2040)
14 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
15 #else
16 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
17 #endif
18
19 #include <hardware/clocks.h>
20 #include <hardware/xosc.h>
21 #include <hardware/structs/rosc.h>
22 #include <hardware/pll.h>
23 #include <hardware/watchdog.h>
24 #include <hardware/resets.h>
25 #include <hardware/ticks.h>
26
27 /* Undefine to prevent conflicts with header definitions */
28 #undef pll_sys
29 #undef pll_usb
30
31 #define CTRL_SRC_LSB CLOCKS_CLK_REF_CTRL_SRC_LSB
32 #define CTRL_SRC_BITS CLOCKS_CLK_REF_CTRL_SRC_BITS
33 #define CTRL_AUXSRC_LSB CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB
34 #define CTRL_AUXSRC_BITS CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS
35 #define CTRL_ENABLE_BITS CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS
36 #define DIV_FRAC_BITS CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS
37 #define DIV_INT_BITS CLOCKS_CLK_GPOUT0_DIV_INT_BITS
38 #define DIV_INT_LSB CLOCKS_CLK_GPOUT0_DIV_INT_LSB
39
40 #define PLL_VCO_FREQ_MIN 750000000
41 #define PLL_VCO_FREQ_MAX 1600000000
42 #define PLL_FB_DIV_MIN 16
43 #define PLL_FB_DIV_MAX 320
44 #define PLL_POST_DIV_MIN 1
45 #define PLL_POST_DIV_MAX 7
46
47 #define ROSC_PHASE_PASSWD_VALUE_PASS _u(0xAA)
48
49 #define STAGE_DS(n) \
50 (COND_CODE_1( \
51 DT_PROP_HAS_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), stage_drive_strength, n), \
52 (DT_PROP_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), stage_drive_strength, n) & \
53 ROSC_FREQA_DS0_BITS), \
54 (0)) \
55 << (n * 3))
56
57 #define CLK_SRC_IS(clk, src) \
58 DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
59 DT_INST_CLOCKS_CTLR_BY_NAME(0, src))
60
61 #define REF_DIV(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), clock_div)
62 #define FB_DIV(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), fb_div)
63 #define POST_DIV1(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), post_div1)
64 #define POST_DIV2(pll) DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), post_div2)
65 #define VCO_FREQ(pll) ((CLOCK_FREQ_xosc / REF_DIV(pll)) * FB_DIV(pll))
66
67 /*
68 * Using the 'clock-names[0]' for expanding macro to frequency value.
69 * The 'clock-names[0]' is set same as label value that given to the node itself.
70 * Use it for traverse clock tree to find root of clock source.
71 */
72 #define CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, clk)
73 #define SRC_CLOCK(clk) DT_STRING_TOKEN_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), \
74 clock_names, 0)
75 #define SRC_CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, SRC_CLOCK(clk))
76
77 #define PLL_FREQ(pll) \
78 (DT_PROP(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), 0), clock_frequency) / \
79 REF_DIV(pll) * FB_DIV(pll) / POST_DIV1(pll) / POST_DIV2(pll))
80
81 #define CLOCK_FREQ_clk_gpout0 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout0), clock_frequency)
82 #define CLOCK_FREQ_clk_gpout1 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout1), clock_frequency)
83 #define CLOCK_FREQ_clk_gpout2 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout2), clock_frequency)
84 #define CLOCK_FREQ_clk_gpout3 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout3), clock_frequency)
85 #define CLOCK_FREQ_clk_hstx DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_hstx), clock_frequency)
86 #define CLOCK_FREQ_clk_ref DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_ref), clock_frequency)
87 #define CLOCK_FREQ_clk_sys DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_sys), clock_frequency)
88 #define CLOCK_FREQ_clk_usb DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_usb), clock_frequency)
89 #define CLOCK_FREQ_clk_adc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_adc), clock_frequency)
90 #define CLOCK_FREQ_clk_rtc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_rtc), clock_frequency)
91 #define CLOCK_FREQ_clk_peri DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_peri), clock_frequency)
92 #define CLOCK_FREQ_xosc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, xosc), clock_frequency)
93 #define CLOCK_FREQ_rosc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_frequency)
94 #define CLOCK_FREQ_rosc_ph DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_frequency)
95 #define CLOCK_FREQ_gpin0 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin0), clock_frequency)
96 #define CLOCK_FREQ_gpin1 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin1), clock_frequency)
97 #define CLOCK_FREQ_pll_sys PLL_FREQ(pll_sys)
98 #define CLOCK_FREQ_pll_usb PLL_FREQ(pll_usb)
99
100 #define CLOCK_AUX_SOURCE(clk) _CONCAT(_CONCAT(AUXSTEM_, clk), _CONCAT(AUXSRC_, SRC_CLOCK(clk)))
101
102 #define AUXSRC_xosc XOSC_CLKSRC
103 #define AUXSRC_rosc ROSC_CLKSRC
104 #define AUXSRC_rosc_ph ROSC_CLKSRC_PH
105 #define AUXSRC_pll_sys CLKSRC_PLL_SYS
106 #define AUXSRC_pll_usb CLKSRC_PLL_USB
107 #define AUXSRC_clk_ref CLK_REF
108 #define AUXSRC_clk_sys CLK_SYS
109 #define AUXSRC_clk_usb CLK_USB
110 #define AUXSRC_clk_adc CLK_ADC
111 #define AUXSRC_clk_gpin0 CLKSRC_GPIN0
112 #define AUXSRC_clk_gpin1 CLKSRC_GPIN1
113 #if defined(CONFIG_SOC_SERIES_RP2040)
114 #define AUXSRC_clk_rtc CLK_RTC
115 #else
116 #define AUXSRC_pll_usb_primary_ref_opcg CLKSRC_PLL_PLL_USB_PRIMARY_REF_OPCG
117 #define AUXSRC_lposc LPOSC_CLKSRC
118 #define AUXSRC_clk_hstx CLK_HSTX
119 #define AUXSRC_otp_clk2fc OTP_CLK2FC
120 #endif
121
122 #define AUXSTEM_clk_gpout0 CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_
123 #define AUXSTEM_clk_gpout1 CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_
124 #define AUXSTEM_clk_gpout2 CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_
125 #define AUXSTEM_clk_gpout3 CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_
126 #define AUXSTEM_clk_ref CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_
127 #define AUXSTEM_clk_sys CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_
128 #define AUXSTEM_clk_usb CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_
129 #define AUXSTEM_clk_adc CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_
130 #define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_
131 #if defined(CONFIG_SOC_SERIES_RP2040)
132 #define AUXSTEM_clk_rtc CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_
133 #else
134 #define AUXSTEM_clk_hstx CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_
135 #endif
136
137 #define TUPLE_ENTRY(n, p, i) \
138 { \
139 _CONCAT(RPI_PICO_CLKID_, DT_INST_STRING_UPPER_TOKEN_BY_IDX(0, clock_names, i)), \
140 COND_CODE_1( \
141 DT_PROP_HAS_IDX(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(clocks), i), \
142 clocks, 0), \
143 (_CONCAT(RPI_PICO_CLKID_, \
144 DT_STRING_UPPER_TOKEN_BY_IDX( \
145 DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(clocks), i), \
146 clock_names, 0))), \
147 (-1)) \
148 }
149
150 enum rpi_pico_clkid {
151 rpi_pico_clkid_none = -1,
152 rpi_pico_clkid_clk_gpout0 = RPI_PICO_CLKID_CLK_GPOUT0,
153 rpi_pico_clkid_clk_gpout1 = RPI_PICO_CLKID_CLK_GPOUT1,
154 rpi_pico_clkid_clk_gpout2 = RPI_PICO_CLKID_CLK_GPOUT2,
155 rpi_pico_clkid_clk_gpout3 = RPI_PICO_CLKID_CLK_GPOUT3,
156 rpi_pico_clkid_clk_ref = RPI_PICO_CLKID_CLK_REF,
157 rpi_pico_clkid_clk_sys = RPI_PICO_CLKID_CLK_SYS,
158 rpi_pico_clkid_clk_peri = RPI_PICO_CLKID_CLK_PERI,
159 rpi_pico_clkid_clk_usb = RPI_PICO_CLKID_CLK_USB,
160 rpi_pico_clkid_clk_adc = RPI_PICO_CLKID_CLK_ADC,
161 #if defined(RPI_PICO_CLKID_CLK_RTC)
162 rpi_pico_clkid_clk_rtc = RPI_PICO_CLKID_CLK_RTC,
163 #endif
164 rpi_pico_clkid_pll_sys = RPI_PICO_CLKID_PLL_SYS,
165 rpi_pico_clkid_pll_usb = RPI_PICO_CLKID_PLL_USB,
166 rpi_pico_clkid_xosc = RPI_PICO_CLKID_XOSC,
167 rpi_pico_clkid_rosc = RPI_PICO_CLKID_ROSC,
168 rpi_pico_clkid_rosc_ph = RPI_PICO_CLKID_ROSC_PH,
169 rpi_pico_clkid_gpin0 = RPI_PICO_CLKID_GPIN0,
170 rpi_pico_clkid_gpin1 = RPI_PICO_CLKID_GPIN1,
171 END_OF_RPI_PICO_CLKID,
172 };
173
174 struct rpi_pico_clkid_tuple {
175 enum rpi_pico_clkid clk;
176 enum rpi_pico_clkid parent;
177 };
178
179 struct rpi_pico_clk_config {
180 uint32_t source;
181 uint32_t aux_source;
182 uint32_t rate;
183 uint32_t source_rate;
184 };
185
186 struct rpi_pico_pll_config {
187 uint32_t ref_div;
188 uint32_t fb_div;
189 uint32_t post_div1;
190 uint32_t post_div2;
191 };
192
193 struct rpi_pico_rosc_config {
194 uint32_t phase;
195 uint32_t range;
196 uint32_t div;
197 uint32_t code;
198 };
199
200 struct rpi_pico_gpin_config {
201 uint32_t frequency;
202 };
203
204 struct clock_control_rpi_pico_config {
205 clocks_hw_t *const clocks_regs;
206 xosc_hw_t *const xosc_regs;
207 pll_hw_t *const pll_sys_regs;
208 pll_hw_t *const pll_usb_regs;
209 rosc_hw_t *const rosc_regs;
210 const struct pinctrl_dev_config *pcfg;
211 struct rpi_pico_pll_config plls_data[RPI_PICO_PLL_COUNT];
212 struct rpi_pico_clk_config clocks_data[RPI_PICO_CLOCK_COUNT];
213 struct rpi_pico_rosc_config rosc_data;
214 struct rpi_pico_gpin_config gpin_data[RPI_PICO_GPIN_COUNT];
215 };
216
217 struct clock_control_rpi_pico_data {
218 uint32_t rosc_freq;
219 uint32_t rosc_ph_freq;
220 };
221
rpi_pico_frequency_count(const struct device * dev,clock_control_subsys_t sys)222 uint64_t rpi_pico_frequency_count(const struct device *dev, clock_control_subsys_t sys)
223 {
224 const struct clock_control_rpi_pico_config *config = dev->config;
225 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
226 fc_hw_t *fc0 = &config->clocks_regs->fc0;
227 uint32_t fc0_id;
228
229 switch (clkid) {
230 case rpi_pico_clkid_clk_ref:
231 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_REF;
232 break;
233 case rpi_pico_clkid_clk_sys:
234 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_SYS;
235 break;
236 case rpi_pico_clkid_clk_peri:
237 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_PERI;
238 break;
239 case rpi_pico_clkid_clk_usb:
240 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_USB;
241 break;
242 case rpi_pico_clkid_clk_adc:
243 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_ADC;
244 break;
245 #if defined(CONFIG_SOC_SERIES_RP2040)
246 case rpi_pico_clkid_clk_rtc:
247 fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_RTC;
248 break;
249 #endif
250 case rpi_pico_clkid_pll_sys:
251 fc0_id = CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY;
252 break;
253 case rpi_pico_clkid_pll_usb:
254 fc0_id = CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY;
255 break;
256 case rpi_pico_clkid_xosc:
257 fc0_id = CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC;
258 break;
259 case rpi_pico_clkid_rosc:
260 fc0_id = CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC;
261 break;
262 case rpi_pico_clkid_rosc_ph:
263 fc0_id = CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH;
264 break;
265 case rpi_pico_clkid_gpin0:
266 fc0_id = CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0;
267 break;
268 case rpi_pico_clkid_gpin1:
269 fc0_id = CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0;
270 break;
271 default:
272 return -1;
273 }
274
275 (void)frequency_count_khz(fc0_id);
276
277 return ((fc0->result >> CLOCKS_FC0_RESULT_KHZ_LSB) * 1000) +
278 ((fc0->result & CLOCKS_FC0_RESULT_FRAC_BITS) * 1000 / CLOCKS_FC0_RESULT_FRAC_BITS);
279 }
280
rpi_pico_rosc_write(const struct device * dev,io_rw_32 * addr,uint32_t value)281 static int rpi_pico_rosc_write(const struct device *dev, io_rw_32 *addr, uint32_t value)
282 {
283 hw_clear_bits(&rosc_hw->status, ROSC_STATUS_BADWRITE_BITS);
284
285 if (rosc_hw->status & ROSC_STATUS_BADWRITE_BITS) {
286 return -EINVAL;
287 }
288
289 *addr = value;
290
291 if (rosc_hw->status & ROSC_STATUS_BADWRITE_BITS) {
292 return -EINVAL;
293 }
294
295 return 0;
296 }
297
298 /**
299 * Get source clock id of this clock
300 *
301 * @param dev pointer to clock device
302 * @param id id of this clock
303 * @return parent clock id
304 */
rpi_pico_get_clock_src(const struct device * dev,enum rpi_pico_clkid id)305 static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum rpi_pico_clkid id)
306 {
307 const struct clock_control_rpi_pico_config *config = dev->config;
308 enum rpi_pico_clkid srcid;
309
310 switch (id) {
311 case rpi_pico_clkid_clk_gpout0:
312 case rpi_pico_clkid_clk_gpout1:
313 case rpi_pico_clkid_clk_gpout2:
314 case rpi_pico_clkid_clk_gpout3: {
315 const static enum rpi_pico_clkid table[] = {
316 rpi_pico_clkid_pll_sys,
317 rpi_pico_clkid_gpin0,
318 rpi_pico_clkid_gpin1,
319 rpi_pico_clkid_pll_usb,
320 rpi_pico_clkid_rosc_ph,
321 rpi_pico_clkid_xosc,
322 rpi_pico_clkid_clk_sys,
323 rpi_pico_clkid_clk_usb,
324 rpi_pico_clkid_clk_adc,
325 #if defined(CONFIG_SOC_SERIES_RP2040)
326 rpi_pico_clkid_clk_rtc,
327 #endif
328 rpi_pico_clkid_clk_ref,
329 };
330
331 clock_hw_t *clock_hw = &config->clocks_regs->clk[id];
332 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
333
334 srcid = table[aux];
335 break;
336 }
337 case rpi_pico_clkid_clk_ref: {
338 const static enum rpi_pico_clkid table[] = {
339 rpi_pico_clkid_pll_usb,
340 rpi_pico_clkid_gpin0,
341 rpi_pico_clkid_gpin1,
342 };
343
344 clock_hw_t *clock_hw = &clocks_hw->clk[id];
345 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
346 uint32_t src = ((clock_hw->ctrl >> CTRL_SRC_LSB) & CTRL_SRC_BITS);
347
348 if (src == CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH) {
349 srcid = rpi_pico_clkid_rosc_ph;
350 } else if (src == CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC) {
351 srcid = rpi_pico_clkid_xosc;
352 } else {
353 srcid = table[aux];
354 }
355 break;
356 }
357 case rpi_pico_clkid_clk_sys: {
358 const static enum rpi_pico_clkid table[] = {
359 rpi_pico_clkid_pll_sys,
360 rpi_pico_clkid_pll_usb,
361 rpi_pico_clkid_rosc,
362 rpi_pico_clkid_xosc,
363 rpi_pico_clkid_gpin0,
364 rpi_pico_clkid_gpin1,
365 };
366
367 clock_hw_t *clock_hw = &clocks_hw->clk[id];
368 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
369 uint32_t src = ((clock_hw->ctrl >> CTRL_SRC_LSB) & CTRL_SRC_BITS);
370
371 if (src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF) {
372 srcid = rpi_pico_clkid_clk_ref;
373 } else {
374 srcid = table[aux];
375 }
376 break;
377 }
378 case rpi_pico_clkid_clk_peri: {
379 const static enum rpi_pico_clkid table[] = {
380 rpi_pico_clkid_clk_sys,
381 rpi_pico_clkid_pll_sys,
382 rpi_pico_clkid_pll_usb,
383 rpi_pico_clkid_rosc_ph,
384 rpi_pico_clkid_xosc,
385 rpi_pico_clkid_gpin0,
386 rpi_pico_clkid_gpin1,
387 };
388
389 clock_hw_t *clock_hw = &clocks_hw->clk[id];
390 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
391
392 srcid = table[aux];
393 break;
394 }
395 case rpi_pico_clkid_clk_usb:
396 case rpi_pico_clkid_clk_adc:
397 #if defined(RPI_PICO_CLKID_CLK_RTC)
398 case rpi_pico_clkid_clk_rtc:
399 #else
400
401 #endif
402 {
403 const static enum rpi_pico_clkid table[] = {
404 rpi_pico_clkid_pll_usb,
405 rpi_pico_clkid_pll_sys,
406 rpi_pico_clkid_rosc_ph,
407 rpi_pico_clkid_xosc,
408 rpi_pico_clkid_gpin0,
409 rpi_pico_clkid_gpin1,
410 };
411
412 clock_hw_t *clock_hw = &clocks_hw->clk[id];
413 uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB);
414
415 srcid = table[aux];
416 break;
417 }
418 case rpi_pico_clkid_pll_sys:
419 case rpi_pico_clkid_pll_usb: {
420 srcid = rpi_pico_clkid_xosc;
421 break;
422 }
423 default:
424 srcid = rpi_pico_clkid_none;
425 break;
426 }
427
428 return srcid;
429 }
430
431 /**
432 * Query clock is enabled or not
433 *
434 * @param dev pointer to clock device
435 * @param id id of clock
436 * @return true if the clock enabled, otherwith false
437 */
rpi_pico_is_clock_enabled(const struct device * dev,enum rpi_pico_clkid id)438 static bool rpi_pico_is_clock_enabled(const struct device *dev, enum rpi_pico_clkid id)
439 {
440 const struct clock_control_rpi_pico_config *config = dev->config;
441
442 if (id == rpi_pico_clkid_clk_sys || id == rpi_pico_clkid_clk_ref) {
443 return true;
444 } else if (id == rpi_pico_clkid_clk_usb ||
445 id == rpi_pico_clkid_clk_peri ||
446 id == rpi_pico_clkid_clk_adc ||
447 #if defined(RPI_PICO_CLKID_CLK_RTC)
448 id == rpi_pico_clkid_clk_rtc ||
449 #endif
450 id == rpi_pico_clkid_clk_gpout0 ||
451 id == rpi_pico_clkid_clk_gpout1 ||
452 id == rpi_pico_clkid_clk_gpout2 ||
453 id == rpi_pico_clkid_clk_gpout3) {
454 clock_hw_t *clock_hw = &config->clocks_regs->clk[id];
455
456 if (clock_hw->ctrl & CTRL_ENABLE_BITS) {
457 return true;
458 }
459 } else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) {
460 pll_hw_t *pll = (id == rpi_pico_clkid_pll_sys) ? config->pll_sys_regs
461 : config->pll_usb_regs;
462
463 if (!(pll->pwr & (PLL_PWR_VCOPD_BITS | PLL_PWR_POSTDIVPD_BITS | PLL_PWR_PD_BITS))) {
464 return true;
465 }
466 } else if (id == rpi_pico_clkid_xosc) {
467 if (config->xosc_regs->status & XOSC_STATUS_ENABLED_BITS) {
468 return true;
469 }
470 } else if (id == rpi_pico_clkid_rosc || id == rpi_pico_clkid_rosc_ph) {
471 return true;
472 }
473
474 return false;
475 }
476
477 /**
478 * Calculate clock frequency with traversing clock tree.
479 *
480 * @param dev pointer to clock device
481 * @param id id of clock
482 * @return frequency value or 0 if disabled
483 */
rpi_pico_calc_clock_freq(const struct device * dev,enum rpi_pico_clkid id)484 static float rpi_pico_calc_clock_freq(const struct device *dev, enum rpi_pico_clkid id)
485 {
486 const struct clock_control_rpi_pico_config *config = dev->config;
487 struct clock_control_rpi_pico_data *data = dev->data;
488 float freq = 0.f;
489
490 if (!rpi_pico_is_clock_enabled(dev, id)) {
491 return freq;
492 }
493
494 if (id == rpi_pico_clkid_clk_sys ||
495 id == rpi_pico_clkid_clk_usb ||
496 id == rpi_pico_clkid_clk_adc ||
497 #if defined(RPI_PICO_CLKID_CLK_RTC)
498 id == rpi_pico_clkid_clk_rtc ||
499 #endif
500 id == rpi_pico_clkid_clk_ref ||
501 id == rpi_pico_clkid_clk_gpout0 ||
502 id == rpi_pico_clkid_clk_gpout1 ||
503 id == rpi_pico_clkid_clk_gpout2 ||
504 id == rpi_pico_clkid_clk_gpout3) {
505 clock_hw_t *clock_hw = &config->clocks_regs->clk[id];
506
507 freq = rpi_pico_calc_clock_freq(dev, rpi_pico_get_clock_src(dev, id)) /
508 (((clock_hw->div & DIV_INT_BITS) >> DIV_INT_LSB) +
509 ((clock_hw->div & DIV_FRAC_BITS) / (float)DIV_FRAC_BITS));
510 } else if (id == rpi_pico_clkid_clk_peri) {
511 freq = rpi_pico_calc_clock_freq(dev, rpi_pico_get_clock_src(dev, id));
512 } else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) {
513 pll_hw_t *pll = (id == rpi_pico_clkid_pll_sys) ? config->pll_sys_regs
514 : config->pll_usb_regs;
515 freq = rpi_pico_calc_clock_freq(dev, rpi_pico_get_clock_src(dev, id)) *
516 (pll->fbdiv_int) / (pll->cs & PLL_CS_REFDIV_BITS) /
517 ((pll->prim & PLL_PRIM_POSTDIV1_BITS) >> PLL_PRIM_POSTDIV1_LSB) /
518 ((pll->prim & PLL_PRIM_POSTDIV2_BITS) >> PLL_PRIM_POSTDIV2_LSB);
519 } else if (id == rpi_pico_clkid_xosc) {
520 freq = CLOCK_FREQ_xosc;
521 } else if (id == rpi_pico_clkid_rosc) {
522 freq = data->rosc_freq;
523 } else if (id == rpi_pico_clkid_rosc_ph) {
524 freq = data->rosc_ph_freq;
525 }
526
527 return freq;
528 }
529
rpi_pico_is_valid_clock_index(enum rpi_pico_clkid index)530 static int rpi_pico_is_valid_clock_index(enum rpi_pico_clkid index)
531 {
532 if (index >= END_OF_RPI_PICO_CLKID) {
533 return -EINVAL;
534 }
535
536 return 0;
537 }
538
clock_control_rpi_pico_on(const struct device * dev,clock_control_subsys_t sys)539 static int clock_control_rpi_pico_on(const struct device *dev, clock_control_subsys_t sys)
540 {
541 const struct clock_control_rpi_pico_config *config = dev->config;
542 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
543
544 if (rpi_pico_is_valid_clock_index(clkid) < 0) {
545 return -EINVAL;
546 }
547
548 switch (clkid) {
549 case rpi_pico_clkid_pll_sys:
550 hw_clear_bits(&config->pll_sys_regs->pwr, PLL_PWR_BITS);
551 break;
552 case rpi_pico_clkid_pll_usb:
553 hw_clear_bits(&config->pll_usb_regs->pwr, PLL_PWR_BITS);
554 break;
555 default:
556 hw_set_bits(&config->clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
557 }
558
559 return 0;
560 }
561
clock_control_rpi_pico_off(const struct device * dev,clock_control_subsys_t sys)562 static int clock_control_rpi_pico_off(const struct device *dev, clock_control_subsys_t sys)
563 {
564 const struct clock_control_rpi_pico_config *config = dev->config;
565 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
566
567 if (rpi_pico_is_valid_clock_index(clkid) < 0) {
568 return -EINVAL;
569 }
570
571 switch (clkid) {
572 case rpi_pico_clkid_pll_sys:
573 hw_set_bits(&config->pll_sys_regs->pwr, PLL_PWR_BITS);
574 break;
575 case rpi_pico_clkid_pll_usb:
576 hw_set_bits(&config->pll_usb_regs->pwr, PLL_PWR_BITS);
577 break;
578 default:
579 hw_clear_bits(&config->clocks_regs->clk[clkid].ctrl, CTRL_ENABLE_BITS);
580 }
581
582 return 0;
583 }
584
clock_control_rpi_pico_get_status(const struct device * dev,clock_control_subsys_t sys)585 static enum clock_control_status clock_control_rpi_pico_get_status(const struct device *dev,
586 clock_control_subsys_t sys)
587 {
588 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
589
590 if (rpi_pico_is_valid_clock_index(clkid) < 0) {
591 return -EINVAL;
592 }
593
594 if (rpi_pico_is_clock_enabled(dev, clkid)) {
595 return CLOCK_CONTROL_STATUS_ON;
596 }
597
598 return CLOCK_CONTROL_STATUS_OFF;
599 }
600
clock_control_rpi_pico_get_rate(const struct device * dev,clock_control_subsys_t sys,uint32_t * rate)601 static int clock_control_rpi_pico_get_rate(const struct device *dev, clock_control_subsys_t sys,
602 uint32_t *rate)
603 {
604 struct clock_control_rpi_pico_data *data = dev->data;
605 enum rpi_pico_clkid clkid = (enum rpi_pico_clkid)sys;
606
607 if (rpi_pico_is_valid_clock_index(clkid) < 0) {
608 return -EINVAL;
609 }
610
611 if (IS_ENABLED(CONFIG_RPI_PICO_ROSC_USE_MEASURED_FREQ)) {
612 if (clkid == rpi_pico_clkid_rosc) {
613 data->rosc_freq = rpi_pico_frequency_count(dev, sys);
614 } else if (clkid == rpi_pico_clkid_rosc_ph) {
615 data->rosc_ph_freq = rpi_pico_frequency_count(dev, sys);
616 }
617 }
618
619 *rate = (int)rpi_pico_calc_clock_freq(dev, clkid);
620
621 return 0;
622 }
623
rpi_pico_clkid_tuple_swap(struct rpi_pico_clkid_tuple * lhs,struct rpi_pico_clkid_tuple * rhs)624 void rpi_pico_clkid_tuple_swap(struct rpi_pico_clkid_tuple *lhs, struct rpi_pico_clkid_tuple *rhs)
625 {
626 struct rpi_pico_clkid_tuple tmp = *lhs;
627 *lhs = *rhs;
628 *rhs = tmp;
629 }
630
rpi_pico_clkid_tuple_reorder_by_dependencies(struct rpi_pico_clkid_tuple * tuples,size_t len)631 void rpi_pico_clkid_tuple_reorder_by_dependencies(struct rpi_pico_clkid_tuple *tuples, size_t len)
632 {
633 uint32_t sorted_idx = 0;
634 uint32_t checked_idx = 0;
635 uint32_t target = -1;
636
637 while (sorted_idx < len) {
638 for (uint32_t i = sorted_idx; i < len; i++) {
639 if (tuples[i].parent == target) {
640 rpi_pico_clkid_tuple_swap(&tuples[sorted_idx], &tuples[i]);
641 sorted_idx++;
642 }
643 }
644 target = tuples[checked_idx++].clk;
645 }
646 }
647
clock_control_rpi_pico_init(const struct device * dev)648 static int clock_control_rpi_pico_init(const struct device *dev)
649 {
650 const uint32_t cycles_per_tick = CLOCK_FREQ_xosc / 1000000;
651 const struct clock_control_rpi_pico_config *config = dev->config;
652 struct clock_control_rpi_pico_data *data = dev->data;
653 clocks_hw_t *clocks_regs = config->clocks_regs;
654 rosc_hw_t *rosc_regs = config->rosc_regs;
655 pll_hw_t *plls[] = {config->pll_sys_regs, config->pll_usb_regs};
656 struct rpi_pico_clkid_tuple tuples[] = {
657 DT_INST_FOREACH_PROP_ELEM_SEP(0, clock_names, TUPLE_ENTRY, (,))};
658 uint32_t rosc_div;
659 int ret;
660
661 /* Reset all function before clock configuring */
662 reset_block(~(RESETS_RESET_IO_QSPI_BITS | RESETS_RESET_PADS_QSPI_BITS |
663 RESETS_RESET_PLL_USB_BITS | RESETS_RESET_USBCTRL_BITS |
664 RESETS_RESET_SYSCFG_BITS | RESETS_RESET_PLL_SYS_BITS));
665
666 unreset_block_wait(RESETS_RESET_BITS &
667 ~(RESETS_RESET_ADC_BITS |
668 #if defined(RESETS_RESET_RTC_BITS)
669 RESETS_RESET_RTC_BITS |
670 #endif
671 #if defined(RESETS_RESET_HSTX_BITS)
672 RESETS_RESET_HSTX_BITS |
673 #endif
674 RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS |
675 RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS |
676 RESETS_RESET_USBCTRL_BITS));
677
678 /* Start tick in watchdog */
679 watchdog_start_tick(cycles_per_tick);
680 #if defined(CONFIG_SOC_SERIES_RP2350)
681 tick_start(TICK_TIMER0, cycles_per_tick);
682 tick_start(TICK_TIMER1, cycles_per_tick);
683 #endif
684
685 clocks_regs->resus.ctrl = 0;
686
687 /* Configure xosc */
688 xosc_init();
689
690 /* Before we touch PLLs, switch sys and ref cleanly away from their aux sources. */
691 clocks_hw->clk[RPI_PICO_CLKID_CLK_SYS].ctrl &= ~CTRL_SRC_BITS;
692 while (clocks_hw->clk[RPI_PICO_CLKID_CLK_SYS].selected != 0x1) {
693 ;
694 }
695 clocks_hw->clk[RPI_PICO_CLKID_CLK_REF].ctrl &= ~CTRL_SRC_BITS;
696 while (clocks_hw->clk[RPI_PICO_CLKID_CLK_REF].selected != 0x1) {
697 ;
698 }
699
700 /* Configure pll */
701 for (uint32_t i = 0; i < RPI_PICO_PLL_COUNT; i++) {
702 pll_init(plls[i], config->plls_data[i].ref_div,
703 CLOCK_FREQ_xosc * config->plls_data[i].fb_div,
704 config->plls_data[i].post_div1, config->plls_data[i].post_div2);
705 }
706
707 /* Configure clocks */
708 rpi_pico_clkid_tuple_reorder_by_dependencies(tuples, ARRAY_SIZE(tuples));
709 for (uint32_t i = 0; i < ARRAY_SIZE(tuples); i++) {
710 if (tuples[i].clk < 0 || tuples[i].clk >= RPI_PICO_CLOCK_COUNT) {
711 continue;
712 }
713
714 if (!(clock_configure(tuples[i].clk, config->clocks_data[tuples[i].clk].source,
715 config->clocks_data[tuples[i].clk].aux_source,
716 config->clocks_data[tuples[i].clk].source_rate,
717 config->clocks_data[tuples[i].clk].rate))) {
718 return -EINVAL;
719 }
720 }
721
722 hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout0].ctrl, CTRL_ENABLE_BITS);
723 hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout1].ctrl, CTRL_ENABLE_BITS);
724 hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout2].ctrl, CTRL_ENABLE_BITS);
725 hw_clear_bits(&clocks_regs->clk[rpi_pico_clkid_clk_gpout3].ctrl, CTRL_ENABLE_BITS);
726
727 /* Configure rosc */
728 ret = rpi_pico_rosc_write(dev, &rosc_regs->phase,
729 (ROSC_PHASE_PASSWD_VALUE_PASS << ROSC_PHASE_PASSWD_LSB) |
730 config->rosc_data.phase);
731 if (ret < 0) {
732 return ret;
733 }
734
735 ret = rpi_pico_rosc_write(dev, &rosc_regs->ctrl,
736 (ROSC_CTRL_ENABLE_VALUE_ENABLE << ROSC_CTRL_ENABLE_LSB) |
737 config->rosc_data.range);
738 if (ret < 0) {
739 return ret;
740 }
741
742 if (config->rosc_data.div <= 0) {
743 rosc_div = ROSC_DIV_VALUE_PASS + 1;
744 } else if (config->rosc_data.div > 31) {
745 rosc_div = ROSC_DIV_VALUE_PASS;
746 } else {
747 rosc_div = ROSC_DIV_VALUE_PASS + config->rosc_data.div;
748 }
749
750 ret = rpi_pico_rosc_write(dev, &rosc_regs->div, rosc_div);
751 if (ret < 0) {
752 return ret;
753 }
754
755 ret = rpi_pico_rosc_write(dev, &rosc_regs->freqa,
756 (ROSC_FREQA_PASSWD_VALUE_PASS << ROSC_FREQA_PASSWD_LSB) |
757 (config->rosc_data.code & UINT16_MAX));
758 if (ret < 0) {
759 return ret;
760 }
761
762 ret = rpi_pico_rosc_write(dev, &rosc_regs->freqb,
763 (ROSC_FREQA_PASSWD_VALUE_PASS << ROSC_FREQA_PASSWD_LSB) |
764 (config->rosc_data.code >> 16));
765 if (ret < 0) {
766 return ret;
767 }
768
769 unreset_block_wait(RESETS_RESET_BITS);
770
771 if (IS_ENABLED(CONFIG_RPI_PICO_ROSC_USE_MEASURED_FREQ)) {
772 data->rosc_freq =
773 rpi_pico_frequency_count(dev, (clock_control_subsys_t)rpi_pico_clkid_rosc);
774 data->rosc_ph_freq = rpi_pico_frequency_count(
775 dev, (clock_control_subsys_t)rpi_pico_clkid_rosc_ph);
776 }
777
778 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
779 if (ret < 0 && ret != -ENOENT) {
780 return ret;
781 }
782
783 return 0;
784 }
785
786 static DEVICE_API(clock_control, clock_control_rpi_pico_api) = {
787 .on = clock_control_rpi_pico_on,
788 .off = clock_control_rpi_pico_off,
789 .get_rate = clock_control_rpi_pico_get_rate,
790 .get_status = clock_control_rpi_pico_get_status,
791 };
792
793 BUILD_ASSERT((VCO_FREQ(pll_sys) >= PLL_VCO_FREQ_MIN) && (VCO_FREQ(pll_sys) <= PLL_VCO_FREQ_MAX) &&
794 (VCO_FREQ(pll_sys) >= (CLOCK_FREQ_xosc / REF_DIV(pll_sys) * 16)),
795 "pll_sys: vco_freq is out of range");
796 BUILD_ASSERT((FB_DIV(pll_sys) >= PLL_FB_DIV_MIN) && (FB_DIV(pll_sys) <= PLL_FB_DIV_MAX),
797 "pll_sys: fb-div is out of range");
798 BUILD_ASSERT((POST_DIV1(pll_sys) >= PLL_POST_DIV_MIN) && (POST_DIV1(pll_sys) <= PLL_POST_DIV_MAX),
799 "pll_sys: post-div1 is out of range");
800 BUILD_ASSERT((POST_DIV2(pll_sys) >= PLL_POST_DIV_MIN) && (POST_DIV2(pll_sys) <= PLL_POST_DIV_MAX),
801 "pll_sys: post-div2 is out of range");
802
803 BUILD_ASSERT((VCO_FREQ(pll_usb) >= PLL_VCO_FREQ_MIN) && (VCO_FREQ(pll_usb) <= PLL_VCO_FREQ_MAX) &&
804 (VCO_FREQ(pll_usb) >= (CLOCK_FREQ_xosc / REF_DIV(pll_usb) * 16)),
805 "pll_usb: vco_freq is out of range");
806 BUILD_ASSERT((FB_DIV(pll_usb) >= PLL_FB_DIV_MIN) && (FB_DIV(pll_usb) <= PLL_FB_DIV_MAX),
807 "pll_usb: fb-div is out of range");
808 BUILD_ASSERT((POST_DIV1(pll_usb) >= PLL_POST_DIV_MIN) && (POST_DIV1(pll_usb) <= PLL_POST_DIV_MAX),
809 "pll_usb: post-div is out of range");
810 BUILD_ASSERT((POST_DIV2(pll_usb) >= PLL_POST_DIV_MIN) && (POST_DIV2(pll_usb) <= PLL_POST_DIV_MAX),
811 "pll_usb: post-div is out of range");
812
813 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_ref) >= CLOCK_FREQ_clk_ref,
814 "clk_ref: clock divider is out of range");
815 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_sys) >= CLOCK_FREQ_clk_sys,
816 "clk_sys: clock divider is out of range");
817 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_usb) >= CLOCK_FREQ_clk_usb,
818 "clk_usb: clock divider is out of range");
819 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_adc) >= CLOCK_FREQ_clk_adc,
820 "clk_adc: clock divider is out of range");
821 #if defined(CONFIG_SOC_SERIES_RP2040)
822 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_rtc) >= CLOCK_FREQ_clk_rtc,
823 "clk_rtc: clock divider is out of range");
824 #endif
825 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_peri) >= CLOCK_FREQ_clk_peri,
826 "clk_peri: clock divider is out of range");
827
828 BUILD_ASSERT(CLOCK_FREQ(rosc_ph) == CLOCK_FREQ(rosc), "rosc_ph: frequency must be equal to rosc");
829
830 PINCTRL_DT_INST_DEFINE(0);
831
832 static const struct clock_control_rpi_pico_config clock_control_rpi_pico_config = {
833 .clocks_regs = (clocks_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, clocks),
834 .xosc_regs = (xosc_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, xosc),
835 .pll_sys_regs = (pll_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, pll_sys),
836 .pll_usb_regs = (pll_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, pll_usb),
837 .rosc_regs = (rosc_hw_t *)DT_INST_REG_ADDR_BY_NAME(0, rosc),
838 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
839 .clocks_data = {
840 [RPI_PICO_CLKID_CLK_GPOUT0] = {
841 .source = 0,
842 .aux_source = CLOCK_AUX_SOURCE(clk_gpout0),
843 .source_rate = SRC_CLOCK_FREQ(clk_gpout0),
844 .rate = CLOCK_FREQ(clk_gpout0),
845 },
846 [RPI_PICO_CLKID_CLK_GPOUT1] = {
847 .source = 0,
848 .aux_source = CLOCK_AUX_SOURCE(clk_gpout1),
849 .source_rate = SRC_CLOCK_FREQ(clk_gpout1),
850 .rate = CLOCK_FREQ(clk_gpout1),
851 },
852 [RPI_PICO_CLKID_CLK_GPOUT2] = {
853 .source = 0,
854 .aux_source = CLOCK_AUX_SOURCE(clk_gpout2),
855 .source_rate = SRC_CLOCK_FREQ(clk_gpout2),
856 .rate = CLOCK_FREQ(clk_gpout2),
857 },
858 [RPI_PICO_CLKID_CLK_GPOUT3] = {
859 .source = 0,
860 .aux_source = CLOCK_AUX_SOURCE(clk_gpout3),
861 .source_rate = SRC_CLOCK_FREQ(clk_gpout3),
862 .rate = CLOCK_FREQ(clk_gpout3),
863 },
864 [RPI_PICO_CLKID_CLK_REF] = {
865 #if CLK_SRC_IS(clk_ref, rosc_ph)
866 .source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH,
867 .aux_source = 0,
868 #elif CLK_SRC_IS(clk_ref, xosc)
869 .source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
870 .aux_source = 0,
871 #else
872 .source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX,
873 #endif
874 .source_rate = SRC_CLOCK_FREQ(clk_ref),
875 .rate = CLOCK_FREQ(clk_ref),
876 },
877 [RPI_PICO_CLKID_CLK_SYS] = {
878 #if CLK_SRC_IS(clk_sys, clk_ref)
879 .source = CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF,
880 .aux_source = 0,
881 #else
882 .source = CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
883 .aux_source = CLOCK_AUX_SOURCE(clk_sys),
884 #endif
885 .source_rate = SRC_CLOCK_FREQ(clk_sys),
886 .rate = CLOCK_FREQ(clk_sys),
887 },
888 [RPI_PICO_CLKID_CLK_PERI] = {
889 .source = 0,
890 .aux_source = CLOCK_AUX_SOURCE(clk_peri),
891 .source_rate = SRC_CLOCK_FREQ(clk_peri),
892 .rate = CLOCK_FREQ(clk_peri),
893 },
894 [RPI_PICO_CLKID_CLK_USB] = {
895 .source = 0,
896 .aux_source = CLOCK_AUX_SOURCE(clk_usb),
897 .source_rate = SRC_CLOCK_FREQ(clk_usb),
898 .rate = CLOCK_FREQ(clk_usb),
899 },
900 [RPI_PICO_CLKID_CLK_ADC] = {
901 .source = 0,
902 .aux_source = CLOCK_AUX_SOURCE(clk_adc),
903 .source_rate = SRC_CLOCK_FREQ(clk_adc),
904 .rate = CLOCK_FREQ(clk_adc),
905 },
906 #if defined(RPI_PICO_CLKID_CLK_RTC)
907 [RPI_PICO_CLKID_CLK_RTC] = {
908 .source = 0,
909 .aux_source = CLOCK_AUX_SOURCE(clk_rtc),
910 .source_rate = SRC_CLOCK_FREQ(clk_rtc),
911 .rate = CLOCK_FREQ(clk_rtc),
912 },
913 #elif defined(RPI_PICO_CLKID_CLK_HSTX)
914 [RPI_PICO_CLKID_CLK_HSTX] = {
915 .source = 0,
916 .aux_source = CLOCK_AUX_SOURCE(clk_hstx),
917 .source_rate = SRC_CLOCK_FREQ(clk_hstx),
918 .rate = CLOCK_FREQ(clk_hstx),
919 },
920 #endif
921 },
922 .plls_data = {
923 [RPI_PICO_PLL_SYS] = {
924 .ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), clock_div),
925 .fb_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), fb_div),
926 .post_div1 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), post_div1),
927 .post_div2 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), post_div2),
928 },
929 [RPI_PICO_PLL_USB] = {
930 .ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), clock_div),
931 .fb_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), fb_div),
932 .post_div1 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), post_div1),
933 .post_div2 = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), post_div2),
934 },
935 },
936 .rosc_data = {
937 .phase = (COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc),
938 phase_flip),
939 (ROSC_PHASE_FLIP_BITS), (0x0)) |
940 COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc),
941 phase),
942 ((DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), phase) &
943 ROSC_PHASE_SHIFT_BITS) | ROSC_PHASE_ENABLE_BITS), (0x0))),
944 .div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), clock_div),
945 .range = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), range),
946 .code = (STAGE_DS(0) | STAGE_DS(1) | STAGE_DS(2) | STAGE_DS(3) |
947 STAGE_DS(4) | STAGE_DS(5) | STAGE_DS(6) | STAGE_DS(7)),
948 },
949 .gpin_data = {
950 [RPI_PICO_GPIN_0] = {
951 COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin0),
952 clock_frequency),
953 (.frequency = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin0),
954 clock_frequency),),
955 (.frequency = 0,))
956 },
957 [RPI_PICO_GPIN_1] = {
958 COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin1),
959 clock_frequency),
960 (.frequency = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, gpin1),
961 clock_frequency),),
962 (.frequency = 0,))
963 },
964 },
965 };
966
967 static struct clock_control_rpi_pico_data clock_control_rpi_pico_data = {
968 .rosc_freq = CLOCK_FREQ(rosc),
969 .rosc_ph_freq = CLOCK_FREQ(rosc_ph),
970 };
971
972 DEVICE_DT_INST_DEFINE(0, clock_control_rpi_pico_init, NULL, &clock_control_rpi_pico_data,
973 &clock_control_rpi_pico_config, PRE_KERNEL_1,
974 CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_rpi_pico_api);
975
