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Searched +full:apb4 +full:- +full:prescaler (Results 1 – 13 of 13) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
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Dst,stm32h7-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
14 "clock-frequency" property.
16 prescaler properties.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
52 - 1
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Dst,stm32h7rs-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
14 "clock-frequency" property.
16 prescaler properties.
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7rs-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
52 - 1
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/Zephyr-latest/dts/bindings/i3c/
Dnuvoton,npcx-i3c.yaml2 # SPDX-License-Identifier: Apache-2.0
11 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
12 core-prescaler = <3>; /* CORE_CLK runs at 30MHz */
13 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
14 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
15 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
16 apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */
30 i3c-scl-hz = <12500000>;
31 i3c-od-scl-hz = <4170000>;
36 compatible: "nuvoton,npcx-i3c"
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/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx4.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx4/npcx4-alts-map.dtsi"
10 #include "npcx4/npcx4-miwus-wui-map.dtsi"
12 #include "npcx4/npcx4-miwus-int-map.dtsi"
14 #include "npcx4/npcx4-espi-vws-map.dtsi"
15 /* npcx4 series low-voltage io controls mapping table */
16 #include "npcx4/npcx4-lvol-ctrl-map.dtsi"
18 #include "zephyr/dt-bindings/reset/npcx4_reset.h"
26 cpu-power-states = <&suspend_to_idle0>;
29 power-states {
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Dnpcx9.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx9/npcx9-alts-map.dtsi"
10 #include "npcx9/npcx9-miwus-wui-map.dtsi"
12 #include "npcx9/npcx9-miwus-int-map.dtsi"
14 #include "npcx9/npcx9-espi-vws-map.dtsi"
15 /* NPCX9 series low-voltage io controls mapping table */
16 #include "npcx9/npcx9-lvol-ctrl-map.dtsi"
24 cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
27 power-states {
28 suspend_to_idle0: suspend-to-idle0 {
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/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_clock.h4 * SPDX-License-Identifier: Apache-2.0
37 /* Core clock prescaler */
38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
42 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
44 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
45 /* APB4 clock divider if supported */
48 #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
50 #error "APB4 clock divider is not supported but defined in pcc node!"
54 /* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
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/Zephyr-latest/dts/arm/st/h7/
Dstm32h7.dtsi7 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
18 #include <zephyr/dt-bindings/reset/stm32h7_reset.h>
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Dstm32h723.dtsi5 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/display/panel.h>
11 #include <zephyr/dt-bindings/flash_controller/ospi.h>
15 compatible = "st,stm32h723", "st,stm32h7", "simple-bus";
17 flash-controller@52002000 {
19 compatible = "st,stm32-nv-flash", "soc-nv-flash";
20 write-block-size = <32>;
21 erase-block-size = <DT_SIZE_K(128)>;
23 max-erase-time = <4000>;
28 compatible = "st,stm32-uart";
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/Zephyr-latest/boards/st/nucleo_h723zg/
Dnucleo_h723zg.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
8 #include <st/h7/stm32h723zgtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 model = "STMicroelectronics STM32H723ZG-NUCLEO board";
19 compatible = "st,stm32h723zg-nucleo";
23 zephyr,shell-uart = &usart3;
31 compatible = "gpio-leds";
47 compatible = "pwm-leds";
51 label = "User LD3 - PWM12";
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/Zephyr-latest/dts/arm/st/h7rs/
Dstm32h7rs.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
13 #include <zephyr/dt-bindings/reset/stm32h7rs_reset.h>
14 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
15 #include <zephyr/dt-bindings/adc/adc.h>
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/Zephyr-latest/dts/arm/st/mp1/
Dstm32mp157.dtsi5 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32_common_clocks.h>
13 #include <zephyr/dt-bindings/clock/stm32_clock.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
17 #include <zephyr/dt-bindings/dma/stm32_dma.h>
18 #include <zephyr/dt-bindings/reset/stm32mp1_reset.h>
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/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h7.c7 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
78 /* SYSCLKSRC before the D1CPRE prescaler */
89 /* ARM Sys CPU Clock before HPRE prescaler */
159 #error "APB4 frequency is too high!"
169 * D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
171 * So, changing this prescaler is not allowed until it is made possible to
174 #error "D1CPRE prescaler can't be higher than 1"
186 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
188 return clock / prescaler; in get_bus_clock()
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