Lines Matching +full:apb4 +full:- +full:prescaler

2 # SPDX-License-Identifier: Apache-2.0
15   "clock-frequency" property.
17   prescaler properties.
21            clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
30   Confere st,stm32-rcc binding for information about domain clocks configuration.
32 compatible: "st,stm32h7rs-rcc"
34 include: [clock-controller.yaml, base.yaml]
40   "#clock-cells":
43   clock-frequency:
53       - 1
54       - 2
55       - 4
56       - 8
57       - 16
58       - 64
59       - 128
60       - 256
61       - 512
63         CPU clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
66         Changing this prescaler is not allowed until it is made possible to
74         divider of the CPU clock by this  prescaler (BMPRE register)
76       - 1
77       - 2
78       - 4
79       - 8
80       - 16
81       - 64
82       - 128
83       - 256
84       - 512
90         APB1 peripheral prescaler
92       - 1
93       - 2
94       - 4
95       - 8
96       - 16
102         APB2 peripheral prescaler
104       - 1
105       - 2
106       - 4
107       - 8
108       - 16
114         APB4 peripheral prescaler
116       - 1
117       - 2
118       - 4
119       - 8
120       - 16
126         APB5 peripheral prescaler
128       - 1
129       - 2
130       - 4
131       - 8
132       - 16
134 clock-cells:
135   - bus
136   - bits