Lines Matching +full:apb4 +full:- +full:prescaler
7 * SPDX-License-Identifier: Apache-2.0
22 /* Macros to fill up prescaler values */
78 /* SYSCLKSRC before the D1CPRE prescaler */
89 /* ARM Sys CPU Clock before HPRE prescaler */
160 #error "APB4 frequency is too high!"
170 * D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
172 * So, changing this prescaler is not allowed until it is made possible to
175 #error "D1CPRE prescaler can't be higher than 1"
187 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
189 return clock / prescaler; in get_bus_clock()
340 return -ERANGE;
382 return -ENOTSUP;
393 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
395 return -ENOTSUP;
400 sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
404 temp = sys_read32(STM32H7_BUS_CLK_REG + pclken->bus);
419 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
421 return -ENOTSUP;
426 sys_clear_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
443 err = enabled_clock(pclken->bus);
451 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
452 STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
453 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
454 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
455 STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
456 STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
469 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
493 switch (pclken->bus) {
582 /* PLL 1 has no T-divider */
645 /* PLL 3 has no T-divider */
649 return -ENOTSUP;
652 if (pclken->div) {
653 *rate /= (pclken->div + 1);
775 * Case of chain-loaded applications:
830 return -ENOTSUP;
1001 switch (RCC->CFGR & RCC_CFGR_SWS) {
1003 sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)
1020 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
1021 pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
1023 if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U) {
1024 pllfracn = (float_t)(uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN)
1034 ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) +
1040 ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) +
1046 hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >>
1049 ((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) +
1054 pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >>
1063 sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
1068 core_presc = (RCC->CDCFGR & RCC_CDCFGR_CPRE);
1071 SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U));
1132 /* Set buses (Sys,AHB, APB1, APB2 & APB4) prescalers */
1170 return -ENOTSUP;