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/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr_heap/src/
Dmain.c29 zassert_equal(0, ret, "Failed initialization"); in ZTEST()
38 * Allocate 0x100 bytes of cacheable memory. in ZTEST()
40 block = mem_attr_heap_alloc(DT_MEM_SW_ALLOC_CACHE, 0x100); in ZTEST()
52 * Allocate 0x100 bytes of non-cacheable memory. in ZTEST()
54 block = mem_attr_heap_alloc(DT_MEM_SW_ALLOC_NON_CACHE, 0x100); in ZTEST()
66 * Allocate 0x100 bytes of DMA memory. in ZTEST()
68 block = mem_attr_heap_alloc(DT_MEM_SW_ALLOC_DMA, 0x100); in ZTEST()
80 * Allocate 0x100 bytes of cacheable and DMA memory. in ZTEST()
82 block = mem_attr_heap_alloc(DT_MEM_SW_ALLOC_CACHE | DT_MEM_SW_ALLOC_DMA, 0x100); in ZTEST()
96 block = mem_attr_heap_alloc(DT_MEM_SW(DT_MEM_SW_ATTR_UNKNOWN), 0x100); in ZTEST()
[all …]
/Zephyr-latest/dts/sparc/gaisler/
Dgr716a.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 reg = <0>;
23 reg = <0x30000000 0x00010000>;
28 reg = <0x31000000 0x00020000>;
40 reg = <0x80002000 0x400>;
49 reg = <0x80003000 0x100>;
55 reg = <0x80300000 0x100>;
62 reg = <0x80301000 0x100>;
69 reg = <0x80302000 0x100>;
[all …]
Dleon3soc.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 reg = <0>;
22 reg = <0x40000000 0x40000000>;
34 reg = <0x80000200 0x100>;
35 eirq = <0>;
43 reg = <0x80000300 0x100>;
49 reg = <0x80000100 0x100>;
/Zephyr-latest/dts/arc/synopsys/
Darc_iot.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
20 reg = <0>;
38 reg = <0xf000a000 0x90>;
43 reg = <0x20000000 0x40000>;
48 reg = <0x80000000 0x20000>;
54 reg = <0x30000000 0x20000>;
57 flash0: flash@0 {
59 reg = <0x0 0x40000>;
65 #clock-cells = <0>;
[all …]
Darc_hs4xd.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
84 reg = <0x90000000 0x50000000>;
90 reg = <0xf0005000 0x1000>;
98 reg = <0xf0026000 0x100>;
107 reg = <0xf0027000 0x100>;
116 reg = <0xf0028000 0x100>;
124 reg = <0xf0003000 0x80>;
136 reg = <0xf00014b0 0x4>;
[all …]
/Zephyr-latest/dts/arm64/intel/
Dintel_socfpga_agilex.dtsi16 #size-cells= <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
27 reg = <0x1>;
33 reg = <0x2>;
39 reg = <0x3>;
45 reg = <0xfffc1000 0x1000>,
46 <0xfffc2000 0x2000>;
67 reg = <0xffd12000 0x1000>;
72 reg = <0xffd10000 0x1000>;
[all …]
Dintel_socfpga_agilex5.dtsi17 #size-cells= <0>;
19 cpu@0 {
23 reg = <0x0>;
30 reg = <0x100>;
37 reg = <0x200>;
44 reg = <0x300>;
50 reg = <0x1d000000 0x10000>, /* GICD */
51 <0x1d060000 0x80000>; /* GICR */
60 reg = <0x1d040000 0x20000>;
76 reg = <0x10d12000 0x1000>;
[all …]
/Zephyr-latest/tests/lib/devicetree/memory_region_flags/
Dapp.overlay7 #address-cells = < 0x1 >;
8 #size-cells = < 0x1 >;
12 reg = < 0x20010000 0x100 >;
19 reg = < 0x20010100 0x100 >;
26 reg = < 0x20010200 0x100 >;
32 reg = < 0x20010300 0x100 >;
/Zephyr-latest/samples/subsys/usb/mass/boards/
Drpi_pico.overlay16 * Usable flash. Starts at 0x100, after the bootloader. The partition
17 * size is 1MB minus the 0x100 bytes taken by the bootloader.
21 reg = <0x100 (DT_SIZE_M(1) - 0x100)>;
27 reg = <0x100000 DT_SIZE_M(1)>;
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4700_F144x2048.dtsi13 reg = <0x1ffe8000 DT_SIZE_K(96)>;
18 reg = <0x20000000 DT_SIZE_K(256)>;
23 reg = <0xc000000 DT_SIZE_M(2)>;
59 gpio-reserved-ranges = <0 2>, <10 2>;
67 reg = <0x48028300 0x100>;
76 reg = <0x48028400 0x100>;
85 reg = <0x48028500 0x100>;
94 reg = <0x48028600 0x100>;
104 reg = <0x48014500 0x100>;
111 reg = <0x48014600 0x100>;
[all …]
/Zephyr-latest/boards/sparkfun/pro_micro_rp2040/
Dsparkfun_pro_micro_rp2040.dts31 /* 16MB of flash minus the 0x100 used for
34 reg = <0x10000000 DT_SIZE_M(16)>;
42 second_stage_bootloader: partition@0 {
44 reg = <0x00000000 0x100>;
50 * Usable flash. Starts at 0x100, after the bootloader. The partition
51 * size is 16MB minus the 0x100 bytes taken by the bootloader.
55 reg = <0x100 (DT_SIZE_M(16) - 0x100)>;
64 pinctrl-0 = <&uart0_default>;
70 pinctrl-0 = <&i2c1_default>;
77 pinctrl-0 = <&spi0_default>;
[all …]
/Zephyr-latest/dts/arm64/ti/
Dti_am62x_a53.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
29 reg = <0x70000000 DT_SIZE_K(64)>;
47 reg = <0x01800000 0x10000>, /* GICD */
48 <0x01880000 0xc0000>; /* GICR */
56 reg = <0x000f4000 0x2ac>;
62 reg = <0x02800000 0x100>;
73 reg = <0x02810000 0x100>;
84 reg = <0x02820000 0x100>;
[all …]
/Zephyr-latest/samples/sensor/qdec/boards/
Dmimxrt1050_evk_mimxrt1052_hyperflash.overlay42 pinctrl-0 = <&pinmux_qdec1>;
50 …xbar-maps = < (21|0x100) (66|0x100) >, /* kXBARA1_InputIomuxXbarIn21 <-> kXBARA1_OutputEnc1PhaseAI…
51 < (22|0x100) (67|0x100) >; /* kXBARA1_InputIomuxXbarIn22 <-> kXBARA1_OutputEnc1PhaseBInput */
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dra4-cm33-common.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
27 reg = <0xe000ed90 0x40>;
37 reg = <0x4001e000 0x1000>;
42 reg = <0x407e0000 0x10000>;
49 reg = <0x40080000 0x20>;
50 port = <0>;
59 reg = <0x40080020 0x20>;
69 reg = <0x40080040 0x20>;
[all …]
Dra4-cm4-common.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
27 reg = <0xe000ed90 0x40>;
36 reg = <0x4001e000 0x1000>;
41 reg = <0x407e0000 0x10000>;
48 reg = <0x40040000 0x20>;
49 port = <0>;
58 reg = <0x40040020 0x20>;
68 reg = <0x40040040 0x20>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dra6-cm33-common.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe000ed90 0x40>;
38 reg = <0x4001e000 0x1000>;
44 reg = <0x40080000 0x20>;
45 port = <0>;
54 reg = <0x40080020 0x20>;
64 reg = <0x40080040 0x20>;
74 reg = <0x40080060 0x20>;
[all …]
Dra6-cm4-common.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe000ed90 0x40>;
37 reg = <0x4001e000 0x1000>;
43 reg = <0x40040000 0x20>;
44 port = <0>;
53 reg = <0x40040020 0x20>;
63 reg = <0x40040040 0x20>;
73 reg = <0x40040060 0x20>;
[all …]
Dr7fa6m4ax.dtsi15 reg = <0x20000000 DT_SIZE_K(256)>;
22 reg = <0x40118100 0x100>;
36 reg = <0x40118200 0x100>;
50 reg = <0x40118300 0x100>;
64 reg = <0x40118400 0x100>;
78 reg = <0x40118500 0x100>;
92 reg = <0x40118600 0x100>;
106 reg = <0x40118700 0x100>;
120 reg = <0x40118800 0x100>;
132 channel-available-mask = <0x33ff>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dra8x1.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe000ed90 0x40>;
38 reg = <0x22000000 DT_SIZE_K(896)>;
43 reg = <0x4001e000 0x1000>;
49 reg = <0x40400800 0x3c0>;
55 reg = <0x40400000 0x20>;
56 port = <0>;
65 reg = <0x40400020 0x20>;
[all …]
/Zephyr-latest/boards/adafruit/kb2040/
Dadafruit_kb2040.dts33 reg = <0x10000000 DT_SIZE_M(8)>;
41 second_stage_bootloader: partition@0 {
43 reg = <0x00000000 0x100>;
48 * Usable flash. Starts at 0x100, after the bootloader. The partition
49 * size is 8MB minus the 0x100 bytes taken by the bootloader.
53 reg = <0x100 (DT_SIZE_M(8) - 0x100)>;
62 pinctrl-0 = <&uart0_default>;
68 pinctrl-0 = <&spi0_default>;
75 pinctrl-0 = <&i2c1_default>;
90 pinctrl-0 = <&adc_default>;
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsame70.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0>;
41 reg = <0xe000ed90 0x40>;
53 reg = <0x400e0600 0x200>;
54 interrupts = <5 0>;
61 reg = <0x400e1810 0x20>;
68 reg = <0x400e0c00 0x200>;
69 interrupts = <6 0>;
85 reg = <0x400e1850 0xc>;
[all …]
/Zephyr-latest/boards/waveshare/rp2040_zero/
Drp2040_zero.dts31 reg = <0x10000000 DT_SIZE_M(16)>;
39 second_stage_bootloader: partition@0 {
41 reg = <0x00000000 0x100>;
46 * Usable flash. Starts at 0x100, after the bootloader. The partition
47 * size is 16MB minus the 0x100 bytes taken by the bootloader.
51 reg = <0x100 (DT_SIZE_M(16) - 0x100)>;
60 pinctrl-0 = <&uart0_default>;
66 pinctrl-0 = <&i2c0_default>;
73 pinctrl-0 = <&i2c1_default>;
81 pinctrl-0 = <&spi0_default>;
[all …]
/Zephyr-latest/boards/adafruit/qt_py_rp2040/
Dadafruit_qt_py_rp2040.dts33 reg = <0x10000000 DT_SIZE_M(8)>;
41 second_stage_bootloader: partition@0 {
43 reg = <0x00000000 0x100>;
48 * Usable flash. Starts at 0x100, after the bootloader. The partition
49 * size is 8MB minus the 0x100 bytes taken by the bootloader.
53 reg = <0x100 (DT_SIZE_M(8) - 0x100)>;
62 pinctrl-0 = <&uart1_default>;
84 pinctrl-0 = <&i2c0_default>;
89 pinctrl-0 = <&i2c1_default>;
98 pinctrl-0 = <&spi0_default>;
[all …]
/Zephyr-latest/boards/wiznet/w5500_evb_pico/
Dw5500_evb_pico.dts31 gpio-map-mask = <0xffffffff 0xffffffc0>;
32 gpio-map-pass-thru = <0 0x3f>;
33 gpio-map = <0 0 &gpio0 0 0>, /* GP0 */
34 <1 0 &gpio0 1 0>, /* GP1 */
35 <2 0 &gpio0 2 0>, /* GP2 */
36 <3 0 &gpio0 3 0>, /* GP3 */
37 <4 0 &gpio0 4 0>, /* GP4 */
38 <5 0 &gpio0 5 0>, /* GP5 */
39 <6 0 &gpio0 6 0>, /* GP6 */
40 <7 0 &gpio0 7 0>, /* GP7 */
[all …]
/Zephyr-latest/subsys/usb/device/
DCMakeLists.txt21 if(CONFIG_USB_DEVICE_VID EQUAL 0x2FE3)
23 "CONFIG_USB_DEVICE_VID has default value 0x2FE3.
27 if(CONFIG_USB_DEVICE_PID EQUAL 0x100)
29 "CONFIG_USB_DEVICE_PID has default value 0x100.

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