Lines Matching +full:0 +full:x100
17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe000ed90 0x40>;
38 reg = <0x4001e000 0x1000>;
44 reg = <0x40080000 0x20>;
45 port = <0>;
54 reg = <0x40080020 0x20>;
64 reg = <0x40080040 0x20>;
74 reg = <0x40080060 0x20>;
84 reg = <0x40080080 0x20>;
94 reg = <0x400800a0 0x20>;
104 reg = <0x40080800 0x3c0>;
110 interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
112 reg = <0x40118000 0x100>;
117 channel = <0>;
126 reg = <0x40118900 0x100>;
138 channel = <0>;
139 reg = <0x4009f000 0x100>;
146 reg = <0x4009f100 0x100>;
153 #size-cells = <0>;
154 channel = <0>;
157 reg = <0x4011a000 0x100>;
164 #size-cells = <0>;
168 reg = <0x4011a100 0x100>;
174 channel = <0>;
175 reg = <0x400e8000 0x100>;
177 renesas,prescaler = <0>;
190 reg = <0x400e8100 0x100>;
192 renesas,prescaler = <0>;
205 reg = <0x400e8200 0x100>;
207 renesas,prescaler = <0>;
220 reg = <0x400e8300 0x100>;
222 renesas,prescaler = <0>;
235 reg = <0x400e8400 0x100>;
237 renesas,prescaler = <0>;
250 reg = <0x400e8500 0x100>;
252 renesas,prescaler = <0>;
266 reg = <0x40170000 0x100>;
276 reg = <0x40170200 0x100>;
284 reg = <0x0100a100 0x18>;
291 reg = <0x0100a134 0xcc>;
298 reg = <0x0100a200 0x100>;
305 reg = <0x40006000 0x1>;
306 channel = <0>;
308 #port-irq-cells = <0>;
314 reg = <0x40006001 0x1>;
317 #port-irq-cells = <0>;
323 reg = <0x40006002 0x1>;
326 #port-irq-cells = <0>;
332 reg = <0x40006003 0x1>;
335 #port-irq-cells = <0>;
341 reg = <0x40006004 0x1>;
344 #port-irq-cells = <0>;
350 reg = <0x40006005 0x1>;
353 #port-irq-cells = <0>;
359 reg = <0x40006006 0x1>;
362 #port-irq-cells = <0>;
368 reg = <0x40006007 0x1>;
371 #port-irq-cells = <0>;
377 reg = <0x40006008 0x1>;
380 #port-irq-cells = <0>;
386 reg = <0x40006009 0x1>;
389 #port-irq-cells = <0>;
395 reg = <0x4000600a 0x1>;
398 #port-irq-cells = <0>;
404 reg = <0x4000600b 0x1>;
407 #port-irq-cells = <0>;
413 reg = <0x4000600c 0x1>;
416 #port-irq-cells = <0>;
422 reg = <0x4000600d 0x1>;
425 #port-irq-cells = <0>;
431 reg = <0x4000600e 0x1>;
434 #port-irq-cells = <0>;
440 reg = <0x4000600f 0x1>;
443 #port-irq-cells = <0>;
452 reg = <0x40169100 0x100>;
462 reg = <0x40169200 0x100>;
472 reg = <0x40169400 0x100>;
482 reg = <0x40169500 0x100>;