1/*
2 * SPDX-License-Identifier: Apache-2.0
3 *
4 * Copyright (C) 2021-2022, Intel Corporation
5 *
6 */
7
8#include <arm64/armv8-a.dtsi>
9#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
11#include <mem.h>
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells= <0>;
17
18		cpu0: cpu@0 {
19			device_type = "cpu";
20			compatible = "arm,cortex-a53";
21			reg = <0>;
22		};
23
24		cpu1: cpu@1 {
25			compatible = "arm,cortex-a53";
26			device_type = "cpu";
27			reg = <0x1>;
28		};
29
30		cpu2: cpu@2 {
31			compatible = "arm,cortex-a53";
32			device_type = "cpu";
33			reg = <0x2>;
34		};
35
36		cpu3: cpu@3 {
37			compatible = "arm,cortex-a53";
38			device_type = "cpu";
39			reg = <0x3>;
40		};
41	};
42
43	gic: interrupt-controller@fffc1000 {
44		compatible = "arm,gic-v2", "arm,gic";
45		reg = <0xfffc1000 0x1000>,
46		      <0xfffc2000 0x2000>;
47		interrupt-controller;
48		#interrupt-cells = <4>;
49		status = "okay";
50	};
51
52	arch_timer: timer {
53		compatible = "arm,armv8-timer";
54		interrupt-parent = <&gic>;
55		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
56			      IRQ_DEFAULT_PRIORITY>,
57			     <GIC_PPI 14 IRQ_TYPE_LEVEL
58			      IRQ_DEFAULT_PRIORITY>,
59			     <GIC_PPI 11 IRQ_TYPE_LEVEL
60			      IRQ_DEFAULT_PRIORITY>,
61			     <GIC_PPI 10 IRQ_TYPE_LEVEL
62			      IRQ_DEFAULT_PRIORITY>;
63	};
64
65	sysmgr: sysmgr@ffd12000 {
66		compatible = "syscon";
67		reg = <0xffd12000 0x1000>;
68	};
69
70	clock: clock@ffd10000 {
71		compatible = "intel,agilex-clock";
72		reg = <0xffd10000 0x1000>;
73		#clock-cells = <1>;
74	};
75
76	/*
77	 * This qspi setting included
78	 * The QSPI controller register and
79	 * The QSPI data register
80	 * QSPI REG  <0xff8d2000 0x100>
81	 * QSPI DATA <0xff900000 0x100000>
82	 */
83	qspi: qspi@ff8d2000 {
84		#address-cells = <0x1>;
85		#size-cells = <0x0>;
86		compatible = "cdns,qspi-nor";
87		reg = <0xff8d2000 0x100>,
88		      <0xff900000 0x100000>;
89		reg-names = "qspi_reg", "qspi_data";
90		interrupt-parent = <&gic>;
91		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL
92			     IRQ_DEFAULT_PRIORITY>;
93		clock-frequency = <50000000>;
94		status = "disabled";
95	};
96
97	mem0: memory@10000000 {
98		device_type = "memory";
99		reg = <0x10000000 0x200000>;
100	};
101
102	fpga0: bridges {
103		compatible = "altr,socfpga-agilex-bridge";
104	};
105
106	uart0: uart@ffc02000 {
107		compatible = "ns16550";
108		reg-shift = <2>;
109		reg = <0xffc02000 0x100>;
110		interrupt-parent = <&gic>;
111		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL
112			      IRQ_DEFAULT_PRIORITY>;
113		interrupt-names = "irq_0";
114		clocks = <&clock INTEL_SOCFPGA_CLOCK_UART>;
115		status = "disabled";
116	};
117
118	sip_smc: smc{
119		compatible = "intel,socfpga-agilex-sip-smc";
120		method = "smc";
121		status = "disabled";
122		zephyr,num-clients = <2>;
123	};
124
125	timer0: timer@ffc03000 {
126		compatible = "snps,dw-timers";
127		interrupt-parent = <&gic>;
128		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL
129				IRQ_DEFAULT_PRIORITY>;
130		reg = <0xffc03000 0x100>;
131		clock-frequency = < 100000000 >;
132		status = "disabled";
133	};
134
135	timer1: timer@ffc03100 {
136		compatible = "snps,dw-timers";
137		interrupt-parent = <&gic>;
138		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL
139				IRQ_DEFAULT_PRIORITY>;
140		reg = <0xffc03100 0x100>;
141		clock-frequency = < 100000000 >;
142		status = "disabled";
143	};
144
145	timer2: timer@ffd00000 {
146		compatible = "snps,dw-timers";
147		interrupt-parent = <&gic>;
148		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL
149				IRQ_DEFAULT_PRIORITY>;
150		reg = <0xffd00000 0x100>;
151		clock-frequency = < 100000000 >;
152		status = "disabled";
153	};
154
155	timer3: timer@ffd00100 {
156		compatible = "snps,dw-timers";
157		interrupt-parent = <&gic>;
158		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL
159				IRQ_DEFAULT_PRIORITY>;
160		reg = <0xffd00100 0x100>;
161		clock-frequency = < 100000000 >;
162	};
163
164	watchdog0: watchdog@ffd00200 {
165		compatible = "snps,designware-watchdog";
166		reg = <0xffd00200 0x100>;
167		clocks = <&clock INTEL_SOCFPGA_CLOCK_WDT>;
168		status = "disabled";
169	};
170
171	watchdog1: watchdog@ffd00300 {
172		compatible = "snps,designware-watchdog";
173		reg = <0xffd00300 0x100>;
174		clocks = <&clock INTEL_SOCFPGA_CLOCK_WDT>;
175		status = "disabled";
176	};
177
178	watchdog2: watchdog@ffd00400 {
179		compatible = "snps,designware-watchdog";
180		reg = <0xffd00400 0x100>;
181		clocks = <&clock INTEL_SOCFPGA_CLOCK_WDT>;
182		status = "disabled";
183	};
184
185	watchdog3: watchdog@ffd00500 {
186		compatible = "snps,designware-watchdog";
187		reg = <0xffd00500 0x100>;
188		clocks = <&clock INTEL_SOCFPGA_CLOCK_WDT>;
189		status = "disabled";
190	};
191};
192