Lines Matching +full:0 +full:x100
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
27 reg = <0xe000ed90 0x40>;
36 reg = <0x4001e000 0x1000>;
41 reg = <0x407e0000 0x10000>;
48 reg = <0x40040000 0x20>;
49 port = <0>;
58 reg = <0x40040020 0x20>;
68 reg = <0x40040040 0x20>;
78 reg = <0x40040060 0x20>;
88 reg = <0x40040080 0x20>;
98 reg = <0x400400a0 0x20>;
108 reg = <0x40040120 0x20>;
118 reg = <0x40040800 0x3c0>;
124 interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
126 reg = <0x40070000 0x20>;
131 channel = <0>;
140 reg = <0x40070020 0x20>;
154 reg = <0x40070120 0x20>;
167 #size-cells = <0>;
168 channel = <0>;
169 reg = <0x40072000 0x100>;
176 #size-cells = <0>;
180 reg = <0x40072100 0x100>;
186 channel = <0>;
187 reg = <0x40084000 0x100>;
189 renesas,prescaler = <0>;
202 reg = <0x40084100 0x100>;
204 renesas,prescaler = <0>;
217 reg = <0x4005c000 0x100>;
226 reg = <0x4005c200 0x100>;
234 channel = <0>;
235 reg = <0x40053000 0x100>;
242 reg = <0x40053100 0x100>;
248 reg = <0x01010018 0x20>;
255 reg = <0x40006000 0x1>;
256 channel = <0>;
258 #port-irq-cells = <0>;
264 reg = <0x40006001 0x1>;
267 #port-irq-cells = <0>;
273 reg = <0x40006002 0x1>;
276 #port-irq-cells = <0>;
282 reg = <0x40006003 0x1>;
285 #port-irq-cells = <0>;
291 reg = <0x40006004 0x1>;
294 #port-irq-cells = <0>;
300 reg = <0x40006006 0x1>;
303 #port-irq-cells = <0>;
309 reg = <0x40006007 0x1>;
312 #port-irq-cells = <0>;
318 reg = <0x40006009 0x1>;
321 #port-irq-cells = <0>;
327 reg = <0x4000600b 0x1>;
330 #port-irq-cells = <0>;
336 reg = <0x4000600e 0x1>;
339 #port-irq-cells = <0>;
345 reg = <0x4000600f 0x1>;
348 #port-irq-cells = <0>;
357 reg = <0x40169000 0x100>;
367 reg = <0x40169100 0x100>;
377 reg = <0x40169200 0x100>;
387 reg = <0x40169300 0x100>;
397 reg = <0x40169400 0x100>;
407 reg = <0x40169500 0x100>;