Lines Matching +full:0 +full:x100
17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe000ed90 0x40>;
38 reg = <0x22000000 DT_SIZE_K(896)>;
43 reg = <0x4001e000 0x1000>;
49 reg = <0x40400800 0x3c0>;
55 reg = <0x40400000 0x20>;
56 port = <0>;
65 reg = <0x40400020 0x20>;
75 reg = <0x40400040 0x20>;
85 reg = <0x40400060 0x20>;
95 reg = <0x40400080 0x20>;
106 reg = <0x404000a0 0x20>;
116 reg = <0x404000c0 0x20>;
126 reg = <0x404000e0 0x20>;
136 reg = <0x40400100 0x20>;
146 reg = <0x40400120 0x20>;
156 reg = <0x40400140 0x20>;
166 reg = <0x40400160 0x20>;
176 channel = <0>;
177 reg = <0x4025E000 0x100>;
185 reg = <0x4025E100 0x100>;
193 reg = <0x40358000 0x100>;
198 channel = <0>;
207 reg = <0x40358100 0x100>;
221 reg = <0x40358200 0x100>;
235 reg = <0x40358300 0x100>;
249 reg = <0x40358400 0x100>;
263 reg = <0x40358900 0x100>;
275 reg = <0x40100000 0x20000>;
286 reg = <0x40332000 0x100>;
290 channel-available-mask = <0xf01f7>;
298 reg = <0x40332200 0x100>;
302 channel-available-mask = <0x7f0077>;
313 #size-cells = <0>;
314 channel = <0>;
319 reg = <0x4035c000 0x100>;
326 #size-cells = <0>;
332 reg = <0x4035c100 0x100>;
341 reg = <0x40322000 0x100>;
351 reg = <0x40322100 0x100>;
361 reg = <0x40322200 0x100>;
371 reg = <0x40322300 0x100>;
381 reg = <0x40322400 0x100>;
391 reg = <0x40322500 0x100>;
401 reg = <0x40322600 0x100>;
411 reg = <0x40322700 0x100>;
421 reg = <0x40322800 0x100>;
431 reg = <0x40322900 0x100>;
441 reg = <0x40322a00 0x100>;
451 reg = <0x40322b00 0x100>;
461 reg = <0x40322c00 0x100>;
471 reg = <0x40322d00 0x100>;
478 reg = <0x0300a100 0x18>;
485 reg = <0x0300a134 0xcc>;
492 reg = <0x0300a200 0x100>;
499 channel = <0>;
500 reg = <0x40221000 0x100>;
504 renesas,prescaler = <0>;
517 reg = <0x40221100 0x100>;
521 renesas,prescaler = <0>;
535 clocks = <&pclka 0 0>, <&pclke 0 0>;
537 reg = <0x40380000 0x4000>;
542 channel = <0>;
563 reg = <0x40354100 0xfc>;
564 interrupts = <42 0>;
573 #size-cells = <0>;
579 reg = <0x40006000 0x1>;
580 channel = <0>;
582 #port-irq-cells = <0>;
588 reg = <0x40006001 0x1>;
591 #port-irq-cells = <0>;
597 reg = <0x40006002 0x1>;
600 #port-irq-cells = <0>;
606 reg = <0x40006003 0x1>;
609 #port-irq-cells = <0>;
615 reg = <0x40006004 0x1>;
618 #port-irq-cells = <0>;
624 reg = <0x40006005 0x1>;
627 #port-irq-cells = <0>;
633 reg = <0x40006006 0x1>;
636 #port-irq-cells = <0>;
642 reg = <0x40006007 0x1>;
645 #port-irq-cells = <0>;
651 reg = <0x40006008 0x1>;
654 #port-irq-cells = <0>;
660 reg = <0x40006009 0x1>;
663 #port-irq-cells = <0>;
669 reg = <0x4000600a 0x1>;
672 #port-irq-cells = <0>;
678 reg = <0x4000600b 0x1>;
681 #port-irq-cells = <0>;
687 reg = <0x4000600c 0x1>;
690 #port-irq-cells = <0>;
696 reg = <0x4000600d 0x1>;
699 #port-irq-cells = <0>;
705 reg = <0x4000600e 0x1>;
708 #port-irq-cells = <0>;
714 reg = <0x4000600f 0x1>;
717 #port-irq-cells = <0>;
723 channel = <0>;
730 reg = <0x40252000 0x0400>;
745 reg = <0x40252400 0x0400>;