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Searched refs:I915_READ (Results 1 – 25 of 59) sorted by relevance

123

/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_workarounds.c598 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | in gen9_gt_workarounds_apply()
603 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in gen9_gt_workarounds_apply()
613 I915_READ(MMCD_MISC_CTRL) | in gen9_gt_workarounds_apply()
619 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in gen9_gt_workarounds_apply()
624 u32 val = I915_READ(GEN8_L3SQCREG1); in gen9_gt_workarounds_apply()
633 I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES); in gen9_gt_workarounds_apply()
646 I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE); in skl_gt_workarounds_apply()
650 I915_READ(GEN7_UCGCTL4) | GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); in skl_gt_workarounds_apply()
655 I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | in skl_gt_workarounds_apply()
669 I915_READ(GEN9_GAMT_ECO_REG_RW_IA) | in bxt_gt_workarounds_apply()
[all …]
Di915_suspend.c36 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
40 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); in i915_save_display()
74 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); in i915_save_state()
77 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); in i915_save_state()
82 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); in i915_save_state()
83 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
86 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); in i915_save_state()
89 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
92 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); in i915_save_state()
93 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
[all …]
Di915_debugfs.c669 I915_READ(GEN8_DE_PIPE_IMR(pipe))); in gen8_display_interrupt_info()
672 I915_READ(GEN8_DE_PIPE_IIR(pipe))); in gen8_display_interrupt_info()
675 I915_READ(GEN8_DE_PIPE_IER(pipe))); in gen8_display_interrupt_info()
681 I915_READ(GEN8_DE_PORT_IMR)); in gen8_display_interrupt_info()
683 I915_READ(GEN8_DE_PORT_IIR)); in gen8_display_interrupt_info()
685 I915_READ(GEN8_DE_PORT_IER)); in gen8_display_interrupt_info()
688 I915_READ(GEN8_DE_MISC_IMR)); in gen8_display_interrupt_info()
690 I915_READ(GEN8_DE_MISC_IIR)); in gen8_display_interrupt_info()
692 I915_READ(GEN8_DE_MISC_IER)); in gen8_display_interrupt_info()
695 I915_READ(GEN8_PCU_IMR)); in gen8_display_interrupt_info()
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Dintel_dpll_mgr.c352 val = I915_READ(PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
354 hw_state->fp0 = I915_READ(PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
355 hw_state->fp1 = I915_READ(PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
378 val = I915_READ(PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
499 val = I915_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
509 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_disable()
524 val = I915_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
541 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_get_hw_state()
933 val = I915_READ(DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
959 I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE); in skl_ddi_pll_enable()
[all …]
Dintel_device_info.c173 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; in gen11_sseu_info_init()
174 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); in gen11_sseu_info_init()
176 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); in gen11_sseu_info_init()
203 const u32 fuse2 = I915_READ(GEN8_FUSE2); in gen10_sseu_info_init()
227 eu_en = ~I915_READ(GEN8_EU_DISABLE0); in gen10_sseu_info_init()
232 eu_en = ~I915_READ(GEN8_EU_DISABLE1); in gen10_sseu_info_init()
239 eu_en = ~I915_READ(GEN8_EU_DISABLE2); in gen10_sseu_info_init()
246 eu_en = ~I915_READ(GEN10_EU_DISABLE3); in gen10_sseu_info_init()
282 fuse = I915_READ(CHV_FUSE_GT); in cherryview_sseu_info_init()
338 fuse2 = I915_READ(GEN8_FUSE2); in gen9_sseu_info_init()
[all …]
Dvlv_dsi.c111 u32 val = I915_READ(reg); in read_data()
265 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
373 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_enable_io()
378 tmp = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
384 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_enable_io()
385 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) in glk_dsi_enable_io()
402 cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & in glk_dsi_enable_io()
425 val = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
430 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
431 val = I915_READ(MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
[all …]
Dintel_engine_cs.c214 cxt_size = I915_READ(GEN7_CXT_SIZE); in __intel_engine_context_size()
218 cxt_size = I915_READ(CXT_SIZE); in __intel_engine_context_size()
753 acthd = I915_READ(RING_ACTHD(engine->mmio_base)); in intel_engine_get_active_head()
755 acthd = I915_READ(ACTHD); in intel_engine_get_active_head()
769 bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); in intel_engine_get_last_batch_head()
902 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); in intel_engine_get_instdone()
907 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); in intel_engine_get_instdone()
918 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); in intel_engine_get_instdone()
923 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); in intel_engine_get_instdone()
924 instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE); in intel_engine_get_instdone()
[all …]
Dintel_audio.c220 tmp = I915_READ(reg_eldv); in intel_eld_uptodate()
226 tmp = I915_READ(reg_elda); in intel_eld_uptodate()
231 if (I915_READ(reg_edid) != *((const u32 *)eld + i)) in intel_eld_uptodate()
246 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_disable()
253 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
271 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_enable()
283 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
293 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
318 tmp = I915_READ(HSW_AUD_CFG(pipe)); in hsw_dp_audio_config_update()
332 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); in hsw_dp_audio_config_update()
[all …]
Dintel_runtime_pm.c342 ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; in hsw_power_well_requesters()
343 ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; in hsw_power_well_requesters()
344 ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; in hsw_power_well_requesters()
345 ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; in hsw_power_well_requesters()
366 wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & in hsw_wait_for_power_well_disable()
408 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); in hsw_power_well_enable()
416 val = I915_READ(CNL_AUX_ANAOVRD1(id)); in hsw_power_well_enable()
436 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); in hsw_power_well_disable()
452 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); in icl_combo_phy_aux_power_well_enable()
455 val = I915_READ(ICL_PORT_CL_DW12(port)); in icl_combo_phy_aux_power_well_enable()
[all …]
Dintel_ddi.c809 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_hdmi()
830 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_dp()
851 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_edp()
877 u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK; in icl_get_combo_buf_trans()
1035 if (I915_READ(reg) & DDI_BUF_IS_IDLE) in intel_wait_ddi_buf_idle()
1182 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1190 temp = I915_READ(DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
1209 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1215 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1224 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
Di915_drv.c2252 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
2253 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
2254 s->arb_mode = I915_READ(ARB_MODE); in vlv_save_gunit_s0ix_state()
2255 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
2256 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
2259 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); in vlv_save_gunit_s0ix_state()
2261 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
2262 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
2264 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
2265 s->ecochk = I915_READ(GAM_ECOCHK); in vlv_save_gunit_s0ix_state()
[all …]
Di915_gpu_error.c1118 error->fence[i] = I915_READ(FENCE_REG(i)); in gem_record_fences()
1128 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base)); in gen6_record_semaphore_state()
1129 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base)); in gen6_record_semaphore_state()
1132 I915_READ(RING_SYNC_2(engine->mmio_base)); in gen6_record_semaphore_state()
1195 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); in error_record_engine_registers()
1197 ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); in error_record_engine_registers()
1200 ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); in error_record_engine_registers()
1205 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); in error_record_engine_registers()
1206 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); in error_record_engine_registers()
1207 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); in error_record_engine_registers()
[all …]
Dintel_panel.c467 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
474 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
483 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
502 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in _vlv_get_backlight()
518 return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller)); in bxt_get_backlight()
535 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
545 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
573 tmp = I915_READ(BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
584 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
672 tmp = I915_READ(BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
[all …]
Di915_irq.c171 u32 val = I915_READ(reg); in gen3_assert_iir_is_zero()
235 val = I915_READ(PORT_HOTPLUG_EN); in i915_hotplug_interrupt_update_locked()
499 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
551 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & in gen9_enable_guc_interrupts()
594 old_val = I915_READ(GEN8_DE_PORT_IMR); in bdw_update_port_irq()
648 uint32_t sdeimr = I915_READ(SDEIMR); in ibx_display_interrupt_update()
876 return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); in g4x_get_vblank_counter()
1124 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); in ironlake_rps_change_irq_handler()
1129 busy_up = I915_READ(RCPREVBSYTUPAVG); in ironlake_rps_change_irq_handler()
1130 busy_down = I915_READ(RCPREVBSYTDNAVG); in ironlake_rps_change_irq_handler()
[all …]
Dintel_cdclk.c237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
406 uint32_t lcpll = I915_READ(LCPLL_CTL); in hsw_get_cdclk()
411 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
515 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
673 uint32_t lcpll = I915_READ(LCPLL_CTL); in bdw_get_cdclk()
678 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
704 if (WARN((I915_READ(LCPLL_CTL) & in bdw_set_cdclk()
721 val = I915_READ(LCPLL_CTL); in bdw_set_cdclk()
729 if (wait_for_us(I915_READ(LCPLL_CTL) & in bdw_set_cdclk()
733 val = I915_READ(LCPLL_CTL); in bdw_set_cdclk()
[all …]
Dintel_crt.c71 val = I915_READ(adpa_reg); in intel_crt_port_enabled()
106 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_flags()
424 save_adpa = adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
446 adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
480 save_adpa = adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
496 adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
546 stat = I915_READ(PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
653 save_bclrpat = I915_READ(bclrpat_reg); in intel_crt_load_detect()
654 save_vtotal = I915_READ(vtotal_reg); in intel_crt_load_detect()
655 vblank = I915_READ(vblank_reg); in intel_crt_load_detect()
[all …]
Dintel_pm.c67 I915_READ(CHICKEN_PAR1_1) | in gen9_init_clock_gating()
73 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
77 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); in gen9_init_clock_gating()
81 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in gen9_init_clock_gating()
86 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in gen9_init_clock_gating()
91 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) in gen9_init_clock_gating()
101 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
108 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
115 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
128 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in glk_init_clock_gating()
[all …]
Dintel_dpio_phy.c277 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
281 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
286 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
296 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
301 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
313 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
316 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
324 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { in bxt_ddi_phy_is_enabled()
336 u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); in bxt_get_grc()
374 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
[all …]
Dintel_display.c530 I915_READ(CLKGATE_DIS_PSL(pipe)) & in skl_wa_clkgate()
1056 line1 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1058 line2 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1111 val = I915_READ(DPLL(pipe)); in assert_pll()
1143 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in assert_fdi_tx()
1146 u32 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx()
1162 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx()
1184 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx_pll_enabled()
1194 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx_pll()
1215 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
[all …]
Dvlv_dsi_pll.c202 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
216 val = I915_READ(BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
239 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_disable()
345 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
366 temp = I915_READ(MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
435 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
545 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_enable()
570 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
577 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1); in bxt_dsi_reset_clocks()
581 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2); in bxt_dsi_reset_clocks()
Dintel_lvds.c91 val = I915_READ(lvds_reg); in intel_lvds_port_enabled()
129 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_config()
147 tmp = I915_READ(PFIT_CONTROL); in intel_lvds_get_config()
160 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
162 val = I915_READ(PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
170 val = I915_READ(PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
176 val = I915_READ(PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
214 val = I915_READ(PP_CONTROL(0)); in intel_lvds_pps_init_hw()
321 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
323 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
[all …]
Dintel_dvo.c129 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
144 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
160 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
182 u32 temp = I915_READ(dvo_reg); in intel_disable_dvo()
186 I915_READ(dvo_reg); in intel_disable_dvo()
196 u32 temp = I915_READ(dvo_reg); in intel_enable_dvo()
203 I915_READ(dvo_reg); in intel_enable_dvo()
276 dvo_val = I915_READ(dvo_reg) & in intel_dvo_pre_enable()
478 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
Di915_vgpu.c209 mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); in intel_vgt_balloon()
210 mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); in intel_vgt_balloon()
211 unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); in intel_vgt_balloon()
212 unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); in intel_vgt_balloon()
Dintel_fifo_underrun.c95 if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
121 if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
143 uint32_t err_int = I915_READ(GEN7_ERR_INT); in ivybridge_check_fifo_underruns()
173 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivybridge_set_fifo_underrun_reporting()
209 uint32_t serr_int = I915_READ(SERR_INT); in cpt_check_pch_fifo_underruns()
241 if (old && I915_READ(SERR_INT) & in cpt_set_fifo_underrun_reporting()
Dintel_psr.c153 u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); in intel_psr_irq_handler()
386 val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; in hsw_activate_psr1()
492 I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) & in intel_psr_compute_config()
530 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); in intel_psr_activate()
531 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); in intel_psr_activate()
559 u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder)); in intel_psr_enable_source()
649 I915_READ(EDP_PSR2_CTL) & in intel_psr_disable_source()
657 I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE); in intel_psr_disable_source()
669 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); in intel_psr_disable_source()
671 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); in intel_psr_disable_source()
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