111 		u32 val = I915_READ(reg);  in read_data()
265 	if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))  in dpi_send_cmd()
373 		tmp = I915_READ(MIPI_CTRL(port));  in glk_dsi_enable_io()
378 	tmp = I915_READ(MIPI_CTRL(PORT_A));  in glk_dsi_enable_io()
384 		tmp = I915_READ(MIPI_CTRL(port));  in glk_dsi_enable_io()
385 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))  in glk_dsi_enable_io()
402 		cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &  in glk_dsi_enable_io()
425 	val = I915_READ(MIPI_CTRL(PORT_A));  in glk_dsi_device_ready()
430 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {  in glk_dsi_device_ready()
431 			val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_device_ready()
438 			val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_device_ready()
449 			val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_device_ready()
455 			val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_device_ready()
460 			val = I915_READ(MIPI_CTRL(port));  in glk_dsi_device_ready()
494 		val = I915_READ(BXT_MIPI_PORT_CTRL(port));  in bxt_dsi_device_ready()
501 		val = I915_READ(MIPI_DEVICE_READY(port));  in bxt_dsi_device_ready()
537 		val = I915_READ(MIPI_PORT_CTRL(PORT_A));  in vlv_dsi_device_ready()
570 		val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_enter_low_power_mode()
601 	tmp = I915_READ(MIPI_CTRL(PORT_A));  in glk_dsi_disable_mipi_io()
615 		tmp = I915_READ(MIPI_CTRL(port));  in glk_dsi_disable_mipi_io()
663 		val = I915_READ(port_ctrl);  in vlv_dsi_clear_device_ready()
684 				temp = I915_READ(MIPI_CTRL(port));  in intel_dsi_port_enable()
691 			temp = I915_READ(VLV_CHICKEN_3);  in intel_dsi_port_enable()
704 		temp = I915_READ(port_ctrl);  in intel_dsi_port_enable()
738 		temp = I915_READ(port_ctrl);  in intel_dsi_port_disable()
827 		val = I915_READ(BXT_P_CR_GT_DISP_PWRON);  in intel_dsi_pre_enable()
840 		val = I915_READ(DSPCLK_GATE_D);  in intel_dsi_pre_enable()
985 		val = I915_READ(BXT_P_CR_GT_DISP_PWRON);  in intel_dsi_post_disable()
997 		val = I915_READ(DSPCLK_GATE_D);  in intel_dsi_post_disable()
1044 		bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;  in intel_dsi_get_hw_state()
1053 			enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;  in intel_dsi_get_hw_state()
1057 			u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));  in intel_dsi_get_hw_state()
1064 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))  in intel_dsi_get_hw_state()
1068 			u32 tmp = I915_READ(MIPI_CTRL(port));  in intel_dsi_get_hw_state()
1116 		if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)  in bxt_dsi_get_pipe_config()
1120 	fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;  in bxt_dsi_get_pipe_config()
1132 				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));  in bxt_dsi_get_pipe_config()
1134 				I915_READ(BXT_MIPI_TRANS_VACTIVE(port));  in bxt_dsi_get_pipe_config()
1136 				I915_READ(BXT_MIPI_TRANS_VTOTAL(port));  in bxt_dsi_get_pipe_config()
1139 	hfp = I915_READ(MIPI_HFP_COUNT(port));  in bxt_dsi_get_pipe_config()
1145 	hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));  in bxt_dsi_get_pipe_config()
1146 	hbp = I915_READ(MIPI_HBP_COUNT(port));  in bxt_dsi_get_pipe_config()
1163 	vfp = I915_READ(MIPI_VFP_COUNT(port));  in bxt_dsi_get_pipe_config()
1164 	vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));  in bxt_dsi_get_pipe_config()
1165 	vbp = I915_READ(MIPI_VBP_COUNT(port));  in bxt_dsi_get_pipe_config()
1430 			tmp = I915_READ(MIPI_CTRL(PORT_A));  in intel_dsi_prepare()
1436 			tmp = I915_READ(MIPI_CTRL(port));  in intel_dsi_prepare()
1443 			tmp = I915_READ(MIPI_CTRL(port));  in intel_dsi_prepare()
1614 		val = I915_READ(MIPI_DSI_FUNC_PRG(port));  in intel_dsi_unprepare()
1700 		val = I915_READ(DSPCNTR(i9xx_plane));  in intel_dsi_get_panel_orientation()