277 	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));  in bxt_ddi_phy_set_signal_level()
281 	val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));  in bxt_ddi_phy_set_signal_level()
286 	val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));  in bxt_ddi_phy_set_signal_level()
296 	val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));  in bxt_ddi_phy_set_signal_level()
301 	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));  in bxt_ddi_phy_set_signal_level()
313 	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))  in bxt_ddi_phy_is_enabled()
316 	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &  in bxt_ddi_phy_is_enabled()
324 	if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {  in bxt_ddi_phy_is_enabled()
336 	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));  in bxt_get_grc()
374 	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);  in _bxt_ddi_phy_init()
393 	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));  in _bxt_ddi_phy_init()
398 	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));  in _bxt_ddi_phy_init()
404 	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));  in _bxt_ddi_phy_init()
410 		val = I915_READ(BXT_PORT_CL2CM_DW6(phy));  in _bxt_ddi_phy_init()
432 		val = I915_READ(BXT_PORT_REF_DW8(phy));  in _bxt_ddi_phy_init()
440 	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));  in _bxt_ddi_phy_init()
452 	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));  in bxt_ddi_phy_uninit()
456 	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);  in bxt_ddi_phy_uninit()
496 	val = I915_READ(reg);  in __phy_reg_verify_state()
599 		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));  in bxt_ddi_phy_set_lane_optim_mask()
627 		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));  in bxt_ddi_phy_get_lane_lat_optim_mask()