Lines Matching refs:I915_READ
71 val = I915_READ(adpa_reg); in intel_crt_port_enabled()
106 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_flags()
424 save_adpa = adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
446 adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
480 save_adpa = adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
496 adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
546 stat = I915_READ(PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
653 save_bclrpat = I915_READ(bclrpat_reg); in intel_crt_load_detect()
654 save_vtotal = I915_READ(vtotal_reg); in intel_crt_load_detect()
655 vblank = I915_READ(vblank_reg); in intel_crt_load_detect()
667 uint32_t pipeconf = I915_READ(pipeconf_reg); in intel_crt_load_detect()
688 uint32_t vsync = I915_READ(vsync_reg); in intel_crt_load_detect()
706 while (I915_READ(pipe_dsl_reg) >= vactive) in intel_crt_load_detect()
708 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) in intel_crt_load_detect()
721 } while ((I915_READ(pipe_dsl_reg) == dsl)); in intel_crt_load_detect()
892 adpa = I915_READ(crt->adpa_reg); in intel_crt_reset()
943 adpa = I915_READ(adpa_reg); in intel_crt_init()
955 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) in intel_crt_init()
1048 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()