237 	tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);  in intel_hpll_vco()
406 	uint32_t lcpll = I915_READ(LCPLL_CTL);  in hsw_get_cdclk()
411 	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)  in hsw_get_cdclk()
515 	WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);  in vlv_program_pfi_credits()
673 	uint32_t lcpll = I915_READ(LCPLL_CTL);  in bdw_get_cdclk()
678 	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)  in bdw_get_cdclk()
704 	if (WARN((I915_READ(LCPLL_CTL) &  in bdw_set_cdclk()
721 	val = I915_READ(LCPLL_CTL);  in bdw_set_cdclk()
729 	if (wait_for_us(I915_READ(LCPLL_CTL) &  in bdw_set_cdclk()
733 	val = I915_READ(LCPLL_CTL);  in bdw_set_cdclk()
756 	val = I915_READ(LCPLL_CTL);  in bdw_set_cdclk()
760 	if (wait_for_us((I915_READ(LCPLL_CTL) &  in bdw_set_cdclk()
823 	val = I915_READ(LCPLL1_CTL);  in skl_dpll0_update()
830 	val = I915_READ(DPLL_CTRL1);  in skl_dpll0_update()
867 	cdctl = I915_READ(CDCLK_CTL);  in skl_get_cdclk()
948 	val = I915_READ(DPLL_CTRL1);  in skl_dpll0_enable()
963 	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);  in skl_dpll0_enable()
978 	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);  in skl_dpll0_disable()
1044 	cdclk_ctl = I915_READ(CDCLK_CTL);  in skl_set_cdclk()
1091 	if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)  in skl_sanitize_cdclk()
1108 	cdctl = I915_READ(CDCLK_CTL);  in skl_sanitize_cdclk()
1263 	val = I915_READ(BXT_DE_PLL_ENABLE);  in bxt_de_pll_update()
1270 	val = I915_READ(BXT_DE_PLL_CTL);  in bxt_de_pll_update()
1287 	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;  in bxt_get_cdclk()
1337 	val = I915_READ(BXT_DE_PLL_CTL);  in bxt_de_pll_enable()
1460 	cdctl = I915_READ(CDCLK_CTL);  in bxt_sanitize_cdclk()
1575 	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)  in cnl_cdclk_pll_update()
1582 	val = I915_READ(BXT_DE_PLL_ENABLE);  in cnl_cdclk_pll_update()
1605 	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;  in cnl_get_cdclk()
1634 	val = I915_READ(BXT_DE_PLL_ENABLE);  in cnl_cdclk_pll_disable()
1639 	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))  in cnl_cdclk_pll_disable()
1657 	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))  in cnl_cdclk_pll_enable()
1767 	cdctl = I915_READ(CDCLK_CTL);  in cnl_sanitize_cdclk()
1916 	val = I915_READ(SKL_DSSM);  in icl_get_cdclk()
1932 	val = I915_READ(BXT_DE_PLL_ENABLE);  in icl_get_cdclk()
1946 	val = I915_READ(CDCLK_CTL);  in icl_get_cdclk()
1982 	val = I915_READ(CDCLK_CTL);  in icl_init_cdclk()
2583 		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;  in intel_update_max_cdclk()
2615 		if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)  in intel_update_max_cdclk()
2667 	if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {  in cnp_rawclk()
2691 	if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {  in icp_rawclk()
2712 	return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;  in pch_rawclk()
2727 	clkcfg = I915_READ(CLKCFG);  in g4x_hrawclk()