342 	ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0;  in hsw_power_well_requesters()
343 	ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0;  in hsw_power_well_requesters()
344 	ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0;  in hsw_power_well_requesters()
345 	ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0;  in hsw_power_well_requesters()
366 	wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &  in hsw_wait_for_power_well_disable()
408 	val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));  in hsw_power_well_enable()
416 		val = I915_READ(CNL_AUX_ANAOVRD1(id));  in hsw_power_well_enable()
436 	val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));  in hsw_power_well_disable()
452 	val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));  in icl_combo_phy_aux_power_well_enable()
455 	val = I915_READ(ICL_PORT_CL_DW12(port));  in icl_combo_phy_aux_power_well_enable()
469 	val = I915_READ(ICL_PORT_CL_DW12(port));  in icl_combo_phy_aux_power_well_disable()
472 	val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));  in icl_combo_phy_aux_power_well_disable()
490 	return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask;  in hsw_power_well_enabled()
497 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),  in assert_can_enable_dc9()
499 	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,  in assert_can_enable_dc9()
501 	WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &  in assert_can_enable_dc9()
520 	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,  in assert_can_disable_dc9()
547 		v = I915_READ(DC_STATE_EN);  in gen9_write_dc_state()
586 	val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);  in gen9_sanitize_dc_state()
624 	val = I915_READ(DC_STATE_EN);  in gen9_set_dc_state()
665 	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),  in assert_csr_loaded()
667 	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");  in assert_csr_loaded()
668 	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");  in assert_csr_loaded()
678 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),  in assert_can_enable_dc5()
693 		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |  in gen9_enable_dc5()
701 	WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,  in assert_can_enable_dc6()
703 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),  in assert_can_enable_dc6()
717 		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |  in skl_enable_dc6()
728 	u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id));  in hsw_power_well_sync_hw()
732 		u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));  in hsw_power_well_sync_hw()
780 	return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;  in gen9_dc_off_power_well_enabled()
785 	u32 tmp = I915_READ(DBUF_CTL);  in gen9_assert_dbuf_enabled()
840 	if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)  in i830_pipes_power_well_enable()
842 	if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)  in i830_pipes_power_well_enable()
856 	return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&  in i830_pipes_power_well_enabled()
857 		I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;  in i830_pipes_power_well_enabled()
963 	val = I915_READ(DSPCLK_GATE_D);  in vlv_init_display_clock_gating()
994 		u32 val = I915_READ(DPLL(pipe));  in vlv_display_power_well_init()
1086 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);  in vlv_dpio_cmn_power_well_enable()
1100 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);  in vlv_dpio_cmn_power_well_disable()
1180 		    (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)  in assert_chv_phy_status()
1229 			  I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,  in assert_chv_phy_status()
2952 	val = I915_READ(reg);  in intel_dbuf_slice_set()
2958 	status = I915_READ(reg) & DBUF_POWER_STATE;  in intel_dbuf_slice_set()
2999 	val = I915_READ(DBUF_CTL_S2);  in icl_dbuf_slices_update()
3011 	I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);  in icl_dbuf_enable()
3012 	I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);  in icl_dbuf_enable()
3017 	if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||  in icl_dbuf_enable()
3018 	    !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))  in icl_dbuf_enable()
3026 	I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);  in icl_dbuf_disable()
3027 	I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);  in icl_dbuf_disable()
3032 	if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||  in icl_dbuf_disable()
3033 	    (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))  in icl_dbuf_disable()
3061 	val = I915_READ(HSW_NDE_RSTWRN_OPT);  in skl_display_core_init()
3128 	val = I915_READ(HSW_NDE_RSTWRN_OPT);  in bxt_display_core_init()
3211 	val = I915_READ(ICL_PORT_COMP_DW3(port));  in cnl_set_procmon_ref_values()
3233 	val = I915_READ(ICL_PORT_COMP_DW1(port));  in cnl_set_procmon_ref_values()
3251 	val = I915_READ(HSW_NDE_RSTWRN_OPT);  in cnl_display_core_init()
3256 	val = I915_READ(CHICKEN_MISC_2);  in cnl_display_core_init()
3263 	val = I915_READ(CNL_PORT_COMP_DW0);  in cnl_display_core_init()
3268 	val = I915_READ(CNL_PORT_CL1CM_DW5);  in cnl_display_core_init()
3320 	val = I915_READ(CHICKEN_MISC_2);  in cnl_display_core_uninit()
3336 	val = I915_READ(HSW_NDE_RSTWRN_OPT);  in icl_display_core_init()
3342 		val = I915_READ(ICL_PHY_MISC(port));  in icl_display_core_init()
3348 		val = I915_READ(ICL_PORT_COMP_DW0(port));  in icl_display_core_init()
3353 		val = I915_READ(ICL_PORT_CL_DW5(port));  in icl_display_core_init()
3377 	I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |  in icl_display_core_init()
3410 		val = I915_READ(ICL_PHY_MISC(port));  in icl_display_core_uninit()
3445 		uint32_t status = I915_READ(DPLL(PIPE_A));  in chv_phy_control_init()
3476 		uint32_t status = I915_READ(DPIO_PHY_STATUS);  in chv_phy_control_init()
3513 	    I915_READ(DPIO_CTL) & DPIO_CMNRST)  in vlv_cmnlane_wa()