67 			   I915_READ(CHICKEN_PAR1_1) |  in gen9_init_clock_gating()
73 		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);  in gen9_init_clock_gating()
77 		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);  in gen9_init_clock_gating()
81 	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |  in gen9_init_clock_gating()
86 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |  in gen9_init_clock_gating()
91 		I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)  in gen9_init_clock_gating()
101 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |  in bxt_init_clock_gating()
108 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |  in bxt_init_clock_gating()
115 	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |  in bxt_init_clock_gating()
128 	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |  in glk_init_clock_gating()
133 		u32 val = I915_READ(CHICKEN_MISC_2);  in glk_init_clock_gating()
146 	tmp = I915_READ(CLKCFG);  in i915_pineview_get_mem_freq()
176 	tmp = I915_READ(CSHRDDR3CTL);  in i915_pineview_get_mem_freq()
356 		was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;  in _intel_set_memory_cxsr()
360 		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;  in _intel_set_memory_cxsr()
364 		val = I915_READ(DSPFW3);  in _intel_set_memory_cxsr()
373 		was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;  in _intel_set_memory_cxsr()
384 		was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;  in _intel_set_memory_cxsr()
484 		dsparb = I915_READ(DSPARB);  in vlv_get_fifo_size()
485 		dsparb2 = I915_READ(DSPARB2);  in vlv_get_fifo_size()
490 		dsparb = I915_READ(DSPARB);  in vlv_get_fifo_size()
491 		dsparb2 = I915_READ(DSPARB2);  in vlv_get_fifo_size()
496 		dsparb2 = I915_READ(DSPARB2);  in vlv_get_fifo_size()
497 		dsparb3 = I915_READ(DSPARB3);  in vlv_get_fifo_size()
515 	uint32_t dsparb = I915_READ(DSPARB);  in i9xx_get_fifo_size()
531 	uint32_t dsparb = I915_READ(DSPARB);  in i830_get_fifo_size()
548 	uint32_t dsparb = I915_READ(DSPARB);  in i845_get_fifo_size()
872 		reg = I915_READ(DSPFW1);  in pineview_update_wm()
882 		reg = I915_READ(DSPFW3);  in pineview_update_wm()
891 		reg = I915_READ(DSPFW3);  in pineview_update_wm()
900 		reg = I915_READ(DSPFW3);  in pineview_update_wm()
2422 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;  in i845_update_wm()
2888 		uint32_t sskpd = I915_READ(MCH_SSKPD);  in intel_read_wm_latency()
2895 		uint32_t mltr = I915_READ(MLTR_ILK);  in intel_read_wm_latency()
3517 			val = I915_READ(WM_MISC);  in ilk_write_wm_values()
3524 			val = I915_READ(DISP_ARB_CTL2);  in ilk_write_wm_values()
3534 		val = I915_READ(DISP_ARB_CTL);  in ilk_write_wm_values()
3581 	if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)  in intel_enabled_dbuf_slices_num()
3894 		val = I915_READ(CUR_BUF_CFG(pipe));  in skl_ddb_get_hw_plane_state()
3900 	val = I915_READ(PLANE_CTL(pipe, plane_id));  in skl_ddb_get_hw_plane_state()
3911 	val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));  in skl_ddb_get_hw_plane_state()
3912 	val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));  in skl_ddb_get_hw_plane_state()
5492 				val = I915_READ(PLANE_WM(pipe, plane_id, level));  in skl_pipe_wm_get_hw_state()
5494 				val = I915_READ(CUR_WM(pipe, level));  in skl_pipe_wm_get_hw_state()
5500 			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));  in skl_pipe_wm_get_hw_state()
5502 			val = I915_READ(CUR_WM_TRANS(pipe));  in skl_pipe_wm_get_hw_state()
5510 	out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));  in skl_pipe_wm_get_hw_state()
5561 	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);  in ilk_pipe_wm_get_hw_state()
5563 		hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));  in ilk_pipe_wm_get_hw_state()
5608 	tmp = I915_READ(DSPFW1);  in g4x_read_wm_values()
5614 	tmp = I915_READ(DSPFW2);  in g4x_read_wm_values()
5622 	tmp = I915_READ(DSPFW3);  in g4x_read_wm_values()
5636 		tmp = I915_READ(VLV_DDL(pipe));  in vlv_read_wm_values()
5648 	tmp = I915_READ(DSPFW1);  in vlv_read_wm_values()
5654 	tmp = I915_READ(DSPFW2);  in vlv_read_wm_values()
5659 	tmp = I915_READ(DSPFW3);  in vlv_read_wm_values()
5663 		tmp = I915_READ(DSPFW7_CHV);  in vlv_read_wm_values()
5667 		tmp = I915_READ(DSPFW8_CHV);  in vlv_read_wm_values()
5671 		tmp = I915_READ(DSPFW9_CHV);  in vlv_read_wm_values()
5675 		tmp = I915_READ(DSPHOWM);  in vlv_read_wm_values()
5687 		tmp = I915_READ(DSPFW7);  in vlv_read_wm_values()
5691 		tmp = I915_READ(DSPHOWM);  in vlv_read_wm_values()
5713 	wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;  in g4x_wm_get_hw_state()
5855 	wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;  in vlv_wm_get_hw_state()
5999 	I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);  in ilk_init_lp_watermarks()
6000 	I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);  in ilk_init_lp_watermarks()
6001 	I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);  in ilk_init_lp_watermarks()
6020 	hw->wm_lp[0] = I915_READ(WM1_LP_ILK);  in ilk_wm_get_hw_state()
6021 	hw->wm_lp[1] = I915_READ(WM2_LP_ILK);  in ilk_wm_get_hw_state()
6022 	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);  in ilk_wm_get_hw_state()
6024 	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);  in ilk_wm_get_hw_state()
6026 		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);  in ilk_wm_get_hw_state()
6027 		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);  in ilk_wm_get_hw_state()
6031 		hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?  in ilk_wm_get_hw_state()
6034 		hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?  in ilk_wm_get_hw_state()
6038 		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);  in ilk_wm_get_hw_state()
6092 	val = I915_READ(DISP_ARB_CTL2);  in intel_enable_ipc()
6151 	rgvmodectl = I915_READ(MEMMODECTL);  in ironlake_enable_drps()
6154 	I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);  in ironlake_enable_drps()
6155 	I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);  in ironlake_enable_drps()
6173 	vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>  in ironlake_enable_drps()
6198 	if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))  in ironlake_enable_drps()
6204 	dev_priv->ips.last_count1 = I915_READ(DMIEC) +  in ironlake_enable_drps()
6205 		I915_READ(DDREC) + I915_READ(CSIEC);  in ironlake_enable_drps()
6207 	dev_priv->ips.last_count2 = I915_READ(GFXEC);  in ironlake_enable_drps()
6222 	I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);  in ironlake_disable_drps()
6224 	I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);  in ironlake_disable_drps()
6226 	I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);  in ironlake_disable_drps()
6681 	rc_ctl = I915_READ(GEN6_RC_CONTROL);  in bxt_check_bios_rc6_setup()
6682 	rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>  in bxt_check_bios_rc6_setup()
6690 	if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {  in bxt_check_bios_rc6_setup()
6699 	rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;  in bxt_check_bios_rc6_setup()
6706 	if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&  in bxt_check_bios_rc6_setup()
6707 	      ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&  in bxt_check_bios_rc6_setup()
6708 	      ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&  in bxt_check_bios_rc6_setup()
6709 	      ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {  in bxt_check_bios_rc6_setup()
6714 	if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||  in bxt_check_bios_rc6_setup()
6715 	    !I915_READ(GEN8_PUSHBUS_ENABLE) ||  in bxt_check_bios_rc6_setup()
6716 	    !I915_READ(GEN8_PUSHBUS_SHIFT)) {  in bxt_check_bios_rc6_setup()
6721 	if (!I915_READ(GEN6_GFXPAUSE)) {  in bxt_check_bios_rc6_setup()
6726 	if (!I915_READ(GEN8_MISC_CTRL0)) {  in bxt_check_bios_rc6_setup()
6768 		u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);  in gen6_init_rps_frequencies()
6773 		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);  in gen6_init_rps_frequencies()
7022 	gtfifodbg = I915_READ(GTFIFODBG);  in gen6_enable_rc6()
7128 	min_ring_freq = I915_READ(DCLK) & 0xf;  in gen6_update_ring_freq()
7298 	unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;  in valleyview_check_pctx()
7308 	unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;  in cherryview_check_pctx()
7319 	pcbr = I915_READ(VLV_PCBR);  in cherryview_setup_pctx()
7329 	DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));  in cherryview_setup_pctx()
7339 	pcbr = I915_READ(VLV_PCBR);  in valleyview_setup_pctx()
7376 	DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));  in valleyview_setup_pctx()
7506 	gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |  in cherryview_enable_rc6()
7542 	pcbr = I915_READ(VLV_PCBR);  in cherryview_enable_rc6()
7603 	gtfifodbg = I915_READ(GTFIFODBG);  in valleyview_enable_rc6()
7727 	count1 = I915_READ(DMIEC);  in __i915_chipset_val()
7728 	count2 = I915_READ(DDREC);  in __i915_chipset_val()
7729 	count3 = I915_READ(CSIEC);  in __i915_chipset_val()
7783 	tsfs = I915_READ(TSFS);  in i915_mch_val()
7830 	count = I915_READ(GFXEC);  in __i915_update_gfx_val()
7867 	pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));  in __i915_gfx_val()
8105 		u32 pxvidfreq = I915_READ(PXVFREQ(i));  in intel_init_emon()
8147 	lcfuse = I915_READ(LCFUSE02);  in intel_init_emon()
8408 			   I915_READ(DSPCNTR(pipe)) |  in g4x_disable_trickle_feed()
8411 		I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));  in g4x_disable_trickle_feed()
8442 		   (I915_READ(ILK_DISPLAY_CHICKEN2) |  in ilk_init_clock_gating()
8446 		   (I915_READ(DISP_ARB_CTL) |  in ilk_init_clock_gating()
8459 			   I915_READ(ILK_DISPLAY_CHICKEN1) |  in ilk_init_clock_gating()
8462 			   I915_READ(ILK_DISPLAY_CHICKEN2) |  in ilk_init_clock_gating()
8469 		   I915_READ(ILK_DISPLAY_CHICKEN2) |  in ilk_init_clock_gating()
8500 	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |  in cpt_init_clock_gating()
8506 		val = I915_READ(TRANS_CHICKEN2(pipe));  in cpt_init_clock_gating()
8527 	tmp = I915_READ(MCH_SSKPD);  in gen6_check_mch_setup()
8540 		   I915_READ(ILK_DISPLAY_CHICKEN2) |  in gen6_init_clock_gating()
8565 		   I915_READ(GEN6_UCGCTL1) |  in gen6_init_clock_gating()
8610 		   I915_READ(ILK_DISPLAY_CHICKEN1) |  in gen6_init_clock_gating()
8613 		   I915_READ(ILK_DISPLAY_CHICKEN2) |  in gen6_init_clock_gating()
8616 		   I915_READ(ILK_DSPCLK_GATE_D) |  in gen6_init_clock_gating()
8629 	uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);  in gen7_setup_fixed_func_scheduler()
8653 			   I915_READ(SOUTH_DSPCLK_GATE_D) |  in lpt_init_clock_gating()
8658 		   I915_READ(TRANS_CHICKEN1(PIPE_A)) |  in lpt_init_clock_gating()
8665 		uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);  in lpt_suspend_hw()
8680 	misccpctl = I915_READ(GEN7_MISCCPCTL);  in gen8_set_l3sqc_credits()
8683 	val = I915_READ(GEN8_L3SQCREG1);  in gen8_set_l3sqc_credits()
8702 		   I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);  in icl_init_clock_gating()
8711 	I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |  in cnp_init_clock_gating()
8726 		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);  in cnl_init_clock_gating()
8729 	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |  in cnl_init_clock_gating()
8732 	val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);  in cnl_init_clock_gating()
8741 	val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);  in cnl_init_clock_gating()
8747 	val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);  in cnl_init_clock_gating()
8758 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |  in cfl_init_clock_gating()
8768 		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |  in kbl_init_clock_gating()
8773 		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |  in kbl_init_clock_gating()
8777 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |  in kbl_init_clock_gating()
8786 	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |  in skl_init_clock_gating()
8790 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |  in skl_init_clock_gating()
8802 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);  in bdw_init_clock_gating()
8806 		   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);  in bdw_init_clock_gating()
8811 			   I915_READ(CHICKEN_PIPESL_1(pipe)) |  in bdw_init_clock_gating()
8818 		   I915_READ(GEN7_FF_THREAD_MODE) &  in bdw_init_clock_gating()
8825 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |  in bdw_init_clock_gating()
8835 	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)  in bdw_init_clock_gating()
8846 		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);  in bdw_init_clock_gating()
8858 			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |  in hsw_init_clock_gating()
8863 		   I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);  in hsw_init_clock_gating()
8892 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);  in hsw_init_clock_gating()
8941 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &  in ivb_init_clock_gating()
8953 			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |  in ivb_init_clock_gating()
8981 	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);  in ivb_init_clock_gating()
9013 	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &  in vlv_init_clock_gating()
9022 		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |  in vlv_init_clock_gating()
9038 		   I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);  in vlv_init_clock_gating()
9077 		   I915_READ(GEN7_FF_THREAD_MODE) &  in chv_init_clock_gating()
9085 	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |  in chv_init_clock_gating()
9089 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |  in chv_init_clock_gating()
9163 	u32 dstate = I915_READ(D_STATE);  in gen3_init_clock_gating()