Lines Matching refs:I915_READ
530 I915_READ(CLKGATE_DIS_PSL(pipe)) & in skl_wa_clkgate()
1056 line1 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1058 line2 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1111 val = I915_READ(DPLL(pipe)); in assert_pll()
1143 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in assert_fdi_tx()
1146 u32 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx()
1162 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx()
1184 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx_pll_enabled()
1194 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx_pll()
1215 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
1242 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
1248 val = I915_READ(pp_reg); in assert_panel_unlocked()
1272 u32 val = I915_READ(PIPECONF(cpu_transcoder)); in assert_pipe()
1321 val = I915_READ(PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
1487 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
1531 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1577 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1579 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1665 I915_READ(dpll_reg) & port_mask, expected_mask); in vlv_wait_port_ready()
1687 val = I915_READ(reg); in ironlake_enable_pch_transcoder()
1693 val = I915_READ(reg); in ironlake_enable_pch_transcoder()
1694 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()
1736 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
1741 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
1772 val = I915_READ(reg); in ironlake_disable_pch_transcoder()
1784 val = I915_READ(reg); in ironlake_disable_pch_transcoder()
1794 val = I915_READ(LPT_TRANSCONF); in lpt_disable_pch_transcoder()
1804 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
1854 val = I915_READ(reg); in intel_enable_pipe()
1893 val = I915_READ(reg); in intel_disable_pipe()
3411 val = I915_READ(DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
3875 temp = I915_READ(reg); in intel_fdi_normal_train()
3886 temp = I915_READ(reg); in intel_fdi_normal_train()
3902 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | in intel_fdi_normal_train()
3922 temp = I915_READ(reg); in ironlake_fdi_link_train()
3926 I915_READ(reg); in ironlake_fdi_link_train()
3931 temp = I915_READ(reg); in ironlake_fdi_link_train()
3939 temp = I915_READ(reg); in ironlake_fdi_link_train()
3954 temp = I915_READ(reg); in ironlake_fdi_link_train()
3968 temp = I915_READ(reg); in ironlake_fdi_link_train()
3974 temp = I915_READ(reg); in ironlake_fdi_link_train()
3984 temp = I915_READ(reg); in ironlake_fdi_link_train()
4020 temp = I915_READ(reg); in gen6_fdi_link_train()
4030 temp = I915_READ(reg); in gen6_fdi_link_train()
4044 temp = I915_READ(reg); in gen6_fdi_link_train()
4059 temp = I915_READ(reg); in gen6_fdi_link_train()
4069 temp = I915_READ(reg); in gen6_fdi_link_train()
4086 temp = I915_READ(reg); in gen6_fdi_link_train()
4097 temp = I915_READ(reg); in gen6_fdi_link_train()
4112 temp = I915_READ(reg); in gen6_fdi_link_train()
4122 temp = I915_READ(reg); in gen6_fdi_link_train()
4153 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
4162 I915_READ(FDI_RX_IIR(pipe))); in ivb_manual_fdi_link_train()
4168 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
4174 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
4182 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
4195 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
4205 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
4209 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { in ivb_manual_fdi_link_train()
4224 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
4230 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
4240 temp = I915_READ(reg); in ivb_manual_fdi_link_train()
4244 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { in ivb_manual_fdi_link_train()
4270 temp = I915_READ(reg); in ironlake_fdi_pll_enable()
4273 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
4280 temp = I915_READ(reg); in ironlake_fdi_pll_enable()
4288 temp = I915_READ(reg); in ironlake_fdi_pll_enable()
4307 temp = I915_READ(reg); in ironlake_fdi_pll_disable()
4312 temp = I915_READ(reg); in ironlake_fdi_pll_disable()
4319 temp = I915_READ(reg); in ironlake_fdi_pll_disable()
4338 temp = I915_READ(reg); in ironlake_fdi_disable()
4343 temp = I915_READ(reg); in ironlake_fdi_disable()
4345 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
4357 temp = I915_READ(reg); in ironlake_fdi_disable()
4363 temp = I915_READ(reg); in ironlake_fdi_disable()
4373 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
4506 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) in lpt_get_iclkip()
4543 I915_READ(HTOTAL(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4545 I915_READ(HBLANK(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4547 I915_READ(HSYNC(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4550 I915_READ(VTOTAL(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4552 I915_READ(VBLANK(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4554 I915_READ(VSYNC(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4556 I915_READ(VSYNCSHIFT(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
4564 temp = I915_READ(SOUTH_CHICKEN1); in cpt_set_fdi_bc_bifurcation()
4568 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
4569 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
4657 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); in ironlake_pch_enable()
4667 temp = I915_READ(PCH_DPLL_SEL); in ironlake_pch_enable()
4698 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
4702 temp = I915_READ(reg); in ironlake_pch_enable()
4747 temp = I915_READ(dslreg); in cpt_verify_modeset()
4749 if (wait_for(I915_READ(dslreg) != temp, 5)) { in cpt_verify_modeset()
4750 if (wait_for(I915_READ(dslreg) != temp, 5)) in cpt_verify_modeset()
5604 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe)); in glk_pipe_scaler_clock_gating_wa()
5705 pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); in haswell_crtc_enable()
5805 temp = I915_READ(reg); in ironlake_crtc_disable()
5812 temp = I915_READ(PCH_DPLL_SEL); in ironlake_crtc_disable()
5871 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); in i9xx_pfit_enable()
6113 I915_READ(PFIT_CONTROL)); in i9xx_pfit_disable()
7327 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); in intel_set_pipe_timings()
7353 tmp = I915_READ(HTOTAL(cpu_transcoder)); in intel_get_pipe_timings()
7356 tmp = I915_READ(HBLANK(cpu_transcoder)); in intel_get_pipe_timings()
7359 tmp = I915_READ(HSYNC(cpu_transcoder)); in intel_get_pipe_timings()
7363 tmp = I915_READ(VTOTAL(cpu_transcoder)); in intel_get_pipe_timings()
7366 tmp = I915_READ(VBLANK(cpu_transcoder)); in intel_get_pipe_timings()
7369 tmp = I915_READ(VSYNC(cpu_transcoder)); in intel_get_pipe_timings()
7373 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { in intel_get_pipe_timings()
7387 tmp = I915_READ(PIPESRC(crtc->pipe)); in intel_get_pipe_src_size()
7427 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
7672 tmp = I915_READ(PFIT_CONTROL); in i9xx_get_pfit_config()
7686 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); in i9xx_get_pfit_config()
7746 val = I915_READ(DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
7760 offset = I915_READ(DSPOFFSET(i9xx_plane)); in i9xx_get_initial_plane_config()
7761 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
7764 offset = I915_READ(DSPTILEOFF(i9xx_plane)); in i9xx_get_initial_plane_config()
7766 offset = I915_READ(DSPLINOFF(i9xx_plane)); in i9xx_get_initial_plane_config()
7767 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
7769 base = I915_READ(DSPADDR(i9xx_plane)); in i9xx_get_initial_plane_config()
7773 val = I915_READ(PIPESRC(pipe)); in i9xx_get_initial_plane_config()
7777 val = I915_READ(DSPSTRIDE(i9xx_plane)); in i9xx_get_initial_plane_config()
7843 tmp = I915_READ(PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
7881 tmp = I915_READ(DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
7888 tmp = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7898 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7908 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
7909 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
7979 u32 temp = I915_READ(PCH_DPLL(i)); in ironlake_init_pch_refclk()
7999 val = I915_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()
8111 tmp = I915_READ(SOUTH_CHICKEN2); in lpt_reset_fdi_mphy()
8115 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & in lpt_reset_fdi_mphy()
8119 tmp = I915_READ(SOUTH_CHICKEN2); in lpt_reset_fdi_mphy()
8123 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & in lpt_reset_fdi_mphy()
8650 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); in intel_pch_transcoder_get_m_n()
8651 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); in intel_pch_transcoder_get_m_n()
8652 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
8654 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); in intel_pch_transcoder_get_m_n()
8655 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
8668 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); in intel_cpu_transcoder_get_m_n()
8669 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); in intel_cpu_transcoder_get_m_n()
8670 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) in intel_cpu_transcoder_get_m_n()
8672 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); in intel_cpu_transcoder_get_m_n()
8673 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) in intel_cpu_transcoder_get_m_n()
8681 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); in intel_cpu_transcoder_get_m_n()
8682 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); in intel_cpu_transcoder_get_m_n()
8683 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) in intel_cpu_transcoder_get_m_n()
8685 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); in intel_cpu_transcoder_get_m_n()
8686 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) in intel_cpu_transcoder_get_m_n()
8690 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
8691 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
8692 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
8694 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
8695 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
8730 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); in skylake_get_pfit_config()
8734 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); in skylake_get_pfit_config()
8735 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); in skylake_get_pfit_config()
8778 val = I915_READ(PLANE_CTL(pipe, plane_id)); in skylake_get_initial_plane_config()
8786 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id)); in skylake_get_initial_plane_config()
8822 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000; in skylake_get_initial_plane_config()
8825 offset = I915_READ(PLANE_OFFSET(pipe, plane_id)); in skylake_get_initial_plane_config()
8827 val = I915_READ(PLANE_SIZE(pipe, plane_id)); in skylake_get_initial_plane_config()
8831 val = I915_READ(PLANE_STRIDE(pipe, plane_id)); in skylake_get_initial_plane_config()
8858 tmp = I915_READ(PF_CTL(crtc->pipe)); in ironlake_get_pfit_config()
8862 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
8863 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
8892 tmp = I915_READ(PIPECONF(crtc->pipe)); in ironlake_get_pipe_config()
8916 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { in ironlake_get_pipe_config()
8922 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); in ironlake_get_pipe_config()
8935 tmp = I915_READ(PCH_DPLL_SEL); in ironlake_get_pipe_config()
8981 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)), in assert_can_disable_lcpll()
8983 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); in assert_can_disable_lcpll()
8984 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); in assert_can_disable_lcpll()
8985 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); in assert_can_disable_lcpll()
8986 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); in assert_can_disable_lcpll()
8987 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
8990 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
8992 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, in assert_can_disable_lcpll()
8994 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, in assert_can_disable_lcpll()
8996 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); in assert_can_disable_lcpll()
9010 return I915_READ(D_COMP_HSW); in hsw_read_dcomp()
9012 return I915_READ(D_COMP_BDW); in hsw_read_dcomp()
9044 val = I915_READ(LCPLL_CTL); in hsw_disable_lcpll()
9050 if (wait_for_us(I915_READ(LCPLL_CTL) & in hsw_disable_lcpll()
9054 val = I915_READ(LCPLL_CTL); in hsw_disable_lcpll()
9074 val = I915_READ(LCPLL_CTL); in hsw_disable_lcpll()
9089 val = I915_READ(LCPLL_CTL); in hsw_restore_lcpll()
9112 val = I915_READ(LCPLL_CTL); in hsw_restore_lcpll()
9122 val = I915_READ(LCPLL_CTL); in hsw_restore_lcpll()
9126 if (wait_for_us((I915_READ(LCPLL_CTL) & in hsw_restore_lcpll()
9167 val = I915_READ(SOUTH_DSPCLK_GATE_D); in hsw_enable_pc8()
9186 val = I915_READ(SOUTH_DSPCLK_GATE_D); in hsw_disable_pc8()
9219 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); in cannonlake_get_ddi_pll()
9239 temp = I915_READ(DPCLKA_CFGCR0_ICL) & in icelake_get_ddi_pll()
9297 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); in skylake_get_ddi_pll()
9311 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); in haswell_get_ddi_pll()
9361 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); in hsw_get_transcoder_state()
9389 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); in hsw_get_transcoder_state()
9427 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); in bxt_get_dsi_transcoder_state()
9431 tmp = I915_READ(MIPI_CTRL(port)); in bxt_get_dsi_transcoder_state()
9450 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); in haswell_get_ddi_port_state()
9477 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { in haswell_get_ddi_port_state()
9480 tmp = I915_READ(FDI_RX_CTL(PIPE_A)); in haswell_get_ddi_port_state()
9524 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; in haswell_get_pipe_config()
9527 u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); in haswell_get_pipe_config()
9554 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; in haswell_get_pipe_config()
9568 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; in haswell_get_pipe_config()
9800 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state()
10025 val = I915_READ(CURCNTR(plane->pipe)); in i9xx_cursor_get_hw_state()
10345 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); in i9xx_crtc_clock_get()
14059 if ((I915_READ(DP_A) & DP_DETECTED) == 0) in has_edp_a()
14062 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) in has_edp_a()
14080 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) in intel_crt_present()
14084 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) in intel_crt_present()
14110 u32 val = I915_READ(PP_CONTROL(pps_idx)); in intel_pps_unlock_regs_wa()
14172 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; in intel_setup_outputs()
14179 found = I915_READ(SFUSE_STRAP); in intel_setup_outputs()
14205 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { in intel_setup_outputs()
14210 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) in intel_setup_outputs()
14214 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) in intel_setup_outputs()
14217 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) in intel_setup_outputs()
14220 if (I915_READ(PCH_DP_C) & DP_DETECTED) in intel_setup_outputs()
14223 if (I915_READ(PCH_DP_D) & DP_DETECTED) in intel_setup_outputs()
14245 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) in intel_setup_outputs()
14247 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) in intel_setup_outputs()
14252 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) in intel_setup_outputs()
14254 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) in intel_setup_outputs()
14263 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) in intel_setup_outputs()
14265 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) in intel_setup_outputs()
14273 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { in intel_setup_outputs()
14287 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { in intel_setup_outputs()
14292 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { in intel_setup_outputs()
14302 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) in intel_setup_outputs()
15124 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; in intel_update_fdi_pll_freq()
15175 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & in intel_modeset_init()
15296 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) | in i830_enable_pipe()
15353 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
15354 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
15355 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
15356 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE); in i830_disable_pipe()
15357 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE); in i830_disable_pipe()
15441 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); in intel_sanitize_crtc()
15544 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { in i915_redisable_vga_power_on()
15771 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in intel_early_display_was()
15780 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); in intel_early_display_was()
16081 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)); in intel_display_capture_error_state()
16090 error->cursor[i].control = I915_READ(CURCNTR(i)); in intel_display_capture_error_state()
16091 error->cursor[i].position = I915_READ(CURPOS(i)); in intel_display_capture_error_state()
16092 error->cursor[i].base = I915_READ(CURBASE(i)); in intel_display_capture_error_state()
16094 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()
16095 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); in intel_display_capture_error_state()
16097 error->plane[i].size = I915_READ(DSPSIZE(i)); in intel_display_capture_error_state()
16098 error->plane[i].pos = I915_READ(DSPPOS(i)); in intel_display_capture_error_state()
16101 error->plane[i].addr = I915_READ(DSPADDR(i)); in intel_display_capture_error_state()
16103 error->plane[i].surface = I915_READ(DSPSURF(i)); in intel_display_capture_error_state()
16104 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); in intel_display_capture_error_state()
16107 error->pipe[i].source = I915_READ(PIPESRC(i)); in intel_display_capture_error_state()
16110 error->pipe[i].stat = I915_READ(PIPESTAT(i)); in intel_display_capture_error_state()
16129 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); in intel_display_capture_error_state()
16130 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); in intel_display_capture_error_state()
16131 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); in intel_display_capture_error_state()
16132 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_display_capture_error_state()
16133 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); in intel_display_capture_error_state()
16134 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); in intel_display_capture_error_state()
16135 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); in intel_display_capture_error_state()