352 	val = I915_READ(PCH_DPLL(id));  in ibx_pch_dpll_get_hw_state()
354 	hw_state->fp0 = I915_READ(PCH_FP0(id));  in ibx_pch_dpll_get_hw_state()
355 	hw_state->fp1 = I915_READ(PCH_FP1(id));  in ibx_pch_dpll_get_hw_state()
378 	val = I915_READ(PCH_DREF_CONTROL);  in ibx_assert_pch_refclk_enabled()
499 	val = I915_READ(WRPLL_CTL(id));  in hsw_ddi_wrpll_disable()
509 	val = I915_READ(SPLL_CTL);  in hsw_ddi_spll_disable()
524 	val = I915_READ(WRPLL_CTL(id));  in hsw_ddi_wrpll_get_hw_state()
541 	val = I915_READ(SPLL_CTL);  in hsw_ddi_spll_get_hw_state()
933 	val = I915_READ(DPLL_CTRL1);  in skl_ddi_pll_write_ctrl1()
959 		   I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);  in skl_ddi_pll_enable()
983 		   I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);  in skl_ddi_pll_disable()
1006 	val = I915_READ(regs[id].ctl);  in skl_ddi_pll_get_hw_state()
1010 	val = I915_READ(DPLL_CTRL1);  in skl_ddi_pll_get_hw_state()
1015 		hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);  in skl_ddi_pll_get_hw_state()
1016 		hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);  in skl_ddi_pll_get_hw_state()
1041 	val = I915_READ(regs[id].ctl);  in skl_ddi_dpll0_get_hw_state()
1045 	val = I915_READ(DPLL_CTRL1);  in skl_ddi_dpll0_get_hw_state()
1453 	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));  in bxt_ddi_pll_enable()
1458 		temp = I915_READ(BXT_PORT_PLL_ENABLE(port));  in bxt_ddi_pll_enable()
1462 		if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &  in bxt_ddi_pll_enable()
1468 	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));  in bxt_ddi_pll_enable()
1473 	temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));  in bxt_ddi_pll_enable()
1479 	temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));  in bxt_ddi_pll_enable()
1485 	temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));  in bxt_ddi_pll_enable()
1491 	temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));  in bxt_ddi_pll_enable()
1497 	temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));  in bxt_ddi_pll_enable()
1503 	temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));  in bxt_ddi_pll_enable()
1511 	temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));  in bxt_ddi_pll_enable()
1516 	temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));  in bxt_ddi_pll_enable()
1521 	temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));  in bxt_ddi_pll_enable()
1528 	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));  in bxt_ddi_pll_enable()
1536 	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));  in bxt_ddi_pll_enable()
1541 	if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),  in bxt_ddi_pll_enable()
1546 		temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));  in bxt_ddi_pll_enable()
1555 	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));  in bxt_ddi_pll_enable()
1568 	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));  in bxt_ddi_pll_disable()
1574 		temp = I915_READ(BXT_PORT_PLL_ENABLE(port));  in bxt_ddi_pll_disable()
1578 		if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &  in bxt_ddi_pll_disable()
1601 	val = I915_READ(BXT_PORT_PLL_ENABLE(port));  in bxt_ddi_pll_get_hw_state()
1605 	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));  in bxt_ddi_pll_get_hw_state()
1608 	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));  in bxt_ddi_pll_get_hw_state()
1611 	hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));  in bxt_ddi_pll_get_hw_state()
1614 	hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));  in bxt_ddi_pll_get_hw_state()
1617 	hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));  in bxt_ddi_pll_get_hw_state()
1620 	hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));  in bxt_ddi_pll_get_hw_state()
1623 	hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));  in bxt_ddi_pll_get_hw_state()
1628 	hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));  in bxt_ddi_pll_get_hw_state()
1631 	hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));  in bxt_ddi_pll_get_hw_state()
1634 	hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));  in bxt_ddi_pll_get_hw_state()
1643 	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));  in bxt_ddi_pll_get_hw_state()
1644 	if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)  in bxt_ddi_pll_get_hw_state()
1647 				 I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));  in bxt_ddi_pll_get_hw_state()
1883 		uint32_t val = I915_READ(LCPLL_CTL);  in intel_ddi_pll_init()
1972 	val = I915_READ(CNL_DPLL_ENABLE(id));  in cnl_ddi_pll_enable()
2013 	val = I915_READ(CNL_DPLL_ENABLE(id));  in cnl_ddi_pll_enable()
2061 	val = I915_READ(CNL_DPLL_ENABLE(id));  in cnl_ddi_pll_disable()
2083 	val = I915_READ(CNL_DPLL_ENABLE(id));  in cnl_ddi_pll_disable()
2109 	val = I915_READ(CNL_DPLL_ENABLE(id));  in cnl_ddi_pll_get_hw_state()
2113 	val = I915_READ(CNL_DPLL_CFGCR0(id));  in cnl_ddi_pll_get_hw_state()
2118 		hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));  in cnl_ddi_pll_get_hw_state()
2537 	cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));  in icl_calc_dp_combo_pll_link()
2538 	cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));  in icl_calc_dp_combo_pll_link()
2934 	val = I915_READ(icl_pll_id_to_enable_reg(id));  in icl_pll_get_hw_state()
2942 		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));  in icl_pll_get_hw_state()
2943 		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));  in icl_pll_get_hw_state()
2950 		hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));  in icl_pll_get_hw_state()
2954 			I915_READ(MG_CLKTOP2_CORECLKCTL1(port));  in icl_pll_get_hw_state()
2959 			I915_READ(MG_CLKTOP2_HSCLKCTL(port));  in icl_pll_get_hw_state()
2966 		hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));  in icl_pll_get_hw_state()
2967 		hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(port));  in icl_pll_get_hw_state()
2968 		hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(port));  in icl_pll_get_hw_state()
2969 		hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));  in icl_pll_get_hw_state()
2970 		hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(port));  in icl_pll_get_hw_state()
2972 		hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(port));  in icl_pll_get_hw_state()
2974 			I915_READ(MG_PLL_TDC_COLDST_BIAS(port));  in icl_pll_get_hw_state()
3021 	val = I915_READ(MG_REFCLKIN_CTL(port));  in icl_mg_pll_write()
3026 	val = I915_READ(MG_CLKTOP2_CORECLKCTL1(port));  in icl_mg_pll_write()
3031 	val = I915_READ(MG_CLKTOP2_HSCLKCTL(port));  in icl_mg_pll_write()
3045 	val = I915_READ(MG_PLL_BIAS(port));  in icl_mg_pll_write()
3050 	val = I915_READ(MG_PLL_TDC_COLDST_BIAS(port));  in icl_mg_pll_write()
3065 	val = I915_READ(enable_reg);  in icl_pll_enable()
3099 	val = I915_READ(enable_reg);  in icl_pll_enable()
3125 	val = I915_READ(enable_reg);  in icl_pll_disable()
3135 	val = I915_READ(enable_reg);  in icl_pll_disable()