809 	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;  in cnl_get_buf_trans_hdmi()
830 	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;  in cnl_get_buf_trans_dp()
851 	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;  in cnl_get_buf_trans_edp()
877 	u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;  in icl_get_combo_buf_trans()
1035 		if (I915_READ(reg) & DDI_BUF_IS_IDLE)  in intel_wait_ddi_buf_idle()
1182 		temp = I915_READ(FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
1190 		temp = I915_READ(DP_TP_STATUS(PORT_E));  in hsw_fdi_link_train()
1209 		temp = I915_READ(DDI_BUF_CTL(PORT_E));  in hsw_fdi_link_train()
1215 		temp = I915_READ(DP_TP_CTL(PORT_E));  in hsw_fdi_link_train()
1224 		temp = I915_READ(FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
1279 	wrpll = I915_READ(reg);  in hsw_ddi_calc_wrpll_link()
1316 	cfgcr1_val = I915_READ(cfgcr1_reg);  in skl_calc_wrpll_link()
1317 	cfgcr2_val = I915_READ(cfgcr2_reg);  in skl_calc_wrpll_link()
1373 		cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));  in cnl_calc_wrpll_link()
1374 		cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));  in cnl_calc_wrpll_link()
1376 		cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));  in cnl_calc_wrpll_link()
1377 		cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));  in cnl_calc_wrpll_link()
1488 	cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));  in cnl_ddi_clock_get()
1542 	dpll_ctl1 = I915_READ(DPLL_CTRL1);  in skl_ddi_clock_get()
1606 		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;  in hsw_ddi_clock_get()
1721 	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));  in intel_ddi_set_vc_payload_alloc()
1821 	uint32_t val = I915_READ(reg);  in intel_ddi_disable_transcoder_func()
1853 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));  in intel_ddi_toggle_hdcp_signalling()
1890 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));  in intel_ddi_connector_get_hw_state()
1940 	tmp = I915_READ(DDI_BUF_CTL(port));  in intel_ddi_get_hw_state()
1946 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));  in intel_ddi_get_hw_state()
1969 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));  in intel_ddi_get_hw_state()
1987 		tmp = I915_READ(BXT_PHY_CTL(port));  in intel_ddi_get_hw_state()
2074 	tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);  in _skl_ddi_set_iboost()
2234 	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));  in cnl_ddi_vswing_program()
2240 	val = I915_READ(CNL_PORT_TX_DW2_LN0(port));  in cnl_ddi_vswing_program()
2252 		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));  in cnl_ddi_vswing_program()
2263 	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));  in cnl_ddi_vswing_program()
2270 	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));  in cnl_ddi_vswing_program()
2299 	val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));  in cnl_ddi_vswing_sequence()
2314 		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));  in cnl_ddi_vswing_sequence()
2325 	val = I915_READ(CNL_PORT_CL1CM_DW5);  in cnl_ddi_vswing_sequence()
2330 	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));  in cnl_ddi_vswing_sequence()
2338 	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));  in cnl_ddi_vswing_sequence()
2361 	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));  in icl_ddi_combo_vswing_program()
2367 	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));  in icl_ddi_combo_vswing_program()
2381 	val = I915_READ(ICL_PORT_TX_DW2_LN0(port));  in icl_ddi_combo_vswing_program()
2393 		val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));  in icl_ddi_combo_vswing_program()
2427 	val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));  in icl_combo_phy_ddi_vswing_sequence()
2442 		val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));  in icl_combo_phy_ddi_vswing_sequence()
2453 	val = I915_READ(ICL_PORT_CL_DW5(port));  in icl_combo_phy_ddi_vswing_sequence()
2458 	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));  in icl_combo_phy_ddi_vswing_sequence()
2466 	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));  in icl_combo_phy_ddi_vswing_sequence()
2559 		val = I915_READ(DPCLKA_CFGCR0_ICL);  in icl_map_plls_to_ports()
2596 			   I915_READ(DPCLKA_CFGCR0_ICL) |  in icl_unmap_plls_to_ports()
2620 		val = I915_READ(DPCLKA_CFGCR0);  in intel_ddi_clk_select()
2630 		val = I915_READ(DPCLKA_CFGCR0);  in intel_ddi_clk_select()
2635 		val = I915_READ(DPLL_CTRL2);  in intel_ddi_clk_select()
2660 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |  in intel_ddi_clk_disable()
2663 		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |  in intel_ddi_clk_disable()
2788 	val = I915_READ(DDI_BUF_CTL(port));  in intel_disable_ddi_buf()
2795 	val = I915_READ(DP_TP_CTL(port));  in intel_disable_ddi_buf()
2896 	val = I915_READ(FDI_RX_CTL(PIPE_A));  in intel_ddi_fdi_post_disable()
2903 	val = I915_READ(FDI_RX_MISC(PIPE_A));  in intel_ddi_fdi_post_disable()
2908 	val = I915_READ(FDI_RX_CTL(PIPE_A));  in intel_ddi_fdi_post_disable()
2912 	val = I915_READ(FDI_RX_CTL(PIPE_A));  in intel_ddi_fdi_post_disable()
2969 		val = I915_READ(CHICKEN_TRANS(transcoder));  in intel_enable_ddi_hdmi()
3082 	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {  in intel_ddi_prepare_link_retrain()
3083 		val = I915_READ(DDI_BUF_CTL(port));  in intel_ddi_prepare_link_retrain()
3090 		val = I915_READ(DP_TP_CTL(port));  in intel_ddi_prepare_link_retrain()
3128 	return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &  in intel_ddi_is_audio_enabled()
3154 	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));  in intel_ddi_get_config()
3522 		if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)  in intel_ddi_max_lanes()
3603 		intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &  in intel_ddi_init()
3606 		intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &  in intel_ddi_init()