Searched refs:pclk (Results 26 – 46 of 46) sorted by relevance
12
| /Zephyr-latest/drivers/serial/ |
| D | uart_ns16550.c | 489 uint32_t pclk) argument
496 return ((pclk + (baud_rate << 3)) / baud_rate) >> 4;
502 uint32_t pclk) argument
522 divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
543 static void set_baud_rate(const struct device *dev, uint32_t baud_rate, uint32_t pclk) argument
550 if ((baud_rate != 0U) && (pclk != 0U)) {
552 divisor = get_ite_uart_baudrate_divisor(dev, baud_rate, pclk);
554 divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
575 uint32_t pclk = 0U; local
618 pclk = dev_cfg->sys_clk_freq;
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| D | uart_lpc11u6x.c | 82 uint32_t pclk; in lpc11u6x_uart0_config_baudrate() local
90 &pclk); in lpc11u6x_uart0_config_baudrate()
91 mul = pclk / (pclk % LPC11U6X_UART0_CLK); in lpc11u6x_uart0_config_baudrate()
93 dl = pclk / (16 * baudrate + 16 * baudrate / mul); in lpc11u6x_uart0_config_baudrate()
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_b91.c | 69 i2c_set_master_clk((unsigned char)(sys_clk.pclk * 1000 * 1000 / (4 * i2c_speed))); in i2c_b91_configure()
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| /Zephyr-latest/dts/arm/silabs/ |
| D | efr32mg21.dtsi | 33 pclk: pclk { label
43 clocks = <&pclk>;
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| D | efr32bg2x.dtsi | 33 pclk: pclk { label
43 clocks = <&pclk>;
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| D | efr32mg24.dtsi | 43 pclk: pclk { label
53 clocks = <&pclk>;
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| D | efr32xg23.dtsi | 43 pclk: pclk { label
53 clocks = <&pclk>;
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| /Zephyr-latest/dts/arm64/fvp/ |
| D | fvp-aemv8r.dtsi | 53 uartclk: apb-pclk {
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| /Zephyr-latest/drivers/counter/ |
| D | counter_gd32_timer.c | 431 uint32_t pclk; in counter_gd32_timer_init() local
436 (clock_control_subsys_t)&cfg->clkid, &pclk); in counter_gd32_timer_init()
438 data->freq = pclk / (cfg->prescaler + 1); in counter_gd32_timer_init()
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| /Zephyr-latest/boards/arm/fvp_base_revc_2xaemv8a/ |
| D | fvp_base_revc_2xaemv8a.dts | 73 uartclk: apb-pclk {
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| /Zephyr-latest/dts/arm64/qemu/ |
| D | qemu-virt-a53.dtsi | 55 uartclk: apb-pclk {
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| D | qemu-virt-arm64.dtsi | 55 uartclk: apb-pclk {
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| /Zephyr-latest/dts/riscv/sifive/ |
| D | riscv64-fu740.dtsi | 23 pclk: p-clk { label
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| /Zephyr-latest/boards/nxp/frdm_mcxn947/ |
| D | frdm_mcxn947.dtsi | 118 pclk-pin = <5>;
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| /Zephyr-latest/drivers/spi/ |
| D | spi_b91.c | 303 uint8_t clk_src = b91_config->peripheral_id == PSPI_MODULE ? sys_clk.pclk : sys_clk.hclk; in spi_b91_config()
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| /Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/ |
| D | sl_clock_manager_tree_config.h | 44 CONCAT(CMU_SYSCLKCTRL_PCLKPRESC_DIV, DT_PROP(DT_NODELABEL(pclk), clock_div))
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| /Zephyr-latest/dts/arm/ambiq/ |
| D | ambiq_apollo4p_blue.dtsi | 11 uartclk: apb-pclk {
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| D | ambiq_apollo3_blue.dtsi | 12 uartclk: apb-pclk {
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| D | ambiq_apollo4p.dtsi | 12 uartclk: apb-pclk {
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| D | ambiq_apollo3p_blue.dtsi | 12 uartclk: apb-pclk {
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-4.0.rst | 460 * Added initial support for Renesas RA clock control driver (:dtcompatible:`renesas,ra-cgc-pclk`,
461 :dtcompatible:`renesas,ra-cgc-pclk-block`, :dtcompatible:`renesas,ra-cgc-pll`,
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