1 /* ns16550.c - NS16550D serial driver */
2
3 #define DT_DRV_COMPAT ns16550
4
5 /*
6 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
7 * Copyright (c) 2020-2023 Intel Corp.
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 */
11
12 /**
13 * @brief NS16550 Serial Driver
14 *
15 * This is the driver for the Intel NS16550 UART Chip used on the PC 386.
16 * It uses the SCCs in asynchronous mode only.
17 *
18 * Before individual UART port can be used, uart_ns16550_port_init() has to be
19 * called to setup the port.
20 */
21
22 #include <errno.h>
23 #include <zephyr/kernel.h>
24 #include <zephyr/arch/cpu.h>
25 #include <zephyr/types.h>
26
27 #include <zephyr/init.h>
28 #include <zephyr/toolchain.h>
29 #include <zephyr/linker/sections.h>
30 #include <zephyr/drivers/uart.h>
31 #include <zephyr/drivers/clock_control.h>
32 #include <zephyr/pm/policy.h>
33 #include <zephyr/sys/sys_io.h>
34 #include <zephyr/spinlock.h>
35 #include <zephyr/irq.h>
36
37 #if defined(CONFIG_PINCTRL)
38 #include <zephyr/drivers/pinctrl.h>
39 #endif
40
41 #include <zephyr/drivers/serial/uart_ns16550.h>
42 #include <zephyr/logging/log.h>
43
44 LOG_MODULE_REGISTER(uart_ns16550, CONFIG_UART_LOG_LEVEL);
45
46 #define UART_NS16550_PCP_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(pcp)
47 #define UART_NS16550_DLF_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(dlf)
48 #define UART_NS16550_DMAS_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(dmas)
49
50 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
51 BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
52 #include <zephyr/drivers/pcie/pcie.h>
53 #endif
54
55 /* Is UART module 'resets' line property defined */
56 #define UART_NS16550_RESET_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
57
58 #if UART_NS16550_RESET_ENABLED
59 #include <zephyr/drivers/reset.h>
60 #endif
61
62 #if defined(CONFIG_UART_ASYNC_API)
63 #include <zephyr/drivers/dma.h>
64 #include <assert.h>
65
66 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
67 #include <zephyr/drivers/dma/dma_intel_lpss.h>
68 #endif
69
70 #endif
71
72 /* If any node has property io-mapped set, we need to support IO port
73 * access in the code and device config struct.
74 *
75 * Note that DT_ANY_INST_HAS_PROP_STATUS_OKAY() always returns true
76 * as io-mapped property is considered always exists and present,
77 * even if its value is zero. Therefore we cannot use it, and has to
78 * resort to the follow helper to see if any okay nodes have io-mapped
79 * as 1.
80 */
81 #define UART_NS16550_DT_PROP_IOMAPPED_HELPER(inst, prop, def) \
82 DT_INST_PROP_OR(inst, prop, def) ||
83
84 #define UART_NS16550_IOPORT_ENABLED \
85 (DT_INST_FOREACH_STATUS_OKAY_VARGS(UART_NS16550_DT_PROP_IOMAPPED_HELPER, io_mapped, 0) 0)
86
87 /* register definitions */
88
89 #define REG_THR 0x00 /* Transmitter holding reg. */
90 #define REG_RDR 0x00 /* Receiver data reg. */
91 #define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
92 #define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
93 #define REG_IER 0x01 /* Interrupt enable reg. */
94 #define REG_IIR 0x02 /* Interrupt ID reg. */
95 #define REG_FCR 0x02 /* FIFO control reg. */
96 #define REG_LCR 0x03 /* Line control reg. */
97 #define REG_MDC 0x04 /* Modem control reg. */
98 #define REG_LSR 0x05 /* Line status reg. */
99 #define REG_MSR 0x06 /* Modem status reg. */
100 #define REG_USR 0x7C /* UART status reg. (DW8250) */
101 #define REG_DLF 0xC0 /* Divisor Latch Fraction */
102 #define REG_PCP 0x200 /* PRV_CLOCK_PARAMS (Apollo Lake) */
103 #define REG_MDR1 0x08 /* Mode control reg. (TI_K3) */
104
105 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
106 #define REG_LPSS_SRC_TRAN 0xAF8 /* SRC Transfer LPSS DMA */
107 #define REG_LPSS_CLR_SRC_TRAN 0xB48 /* Clear SRC Tran LPSS DMA */
108 #define REG_LPSS_MST 0xB20 /* Mask SRC Transfer LPSS DMA */
109 #endif
110
111 /* equates for interrupt enable register */
112
113 #define IER_RXRDY 0x01 /* receiver data ready */
114 #define IER_TBE 0x02 /* transmit bit enable */
115 #define IER_LSR 0x04 /* line status interrupts */
116 #define IER_MSI 0x08 /* modem status interrupts */
117
118 /* equates for interrupt identification register */
119
120 #define IIR_MSTAT 0x00 /* modem status interrupt */
121 #define IIR_NIP 0x01 /* no interrupt pending */
122 #define IIR_THRE 0x02 /* transmit holding register empty interrupt */
123 #define IIR_RBRF 0x04 /* receiver buffer register full interrupt */
124 #define IIR_LS 0x06 /* receiver line status interrupt */
125 #define IIR_MASK 0x07 /* interrupt id bits mask */
126 #define IIR_ID 0x06 /* interrupt ID mask without NIP */
127 #define IIR_BUSY 0x07 /* DesignWare APB busy detect */
128 #define IIR_FE 0xC0 /* FIFO mode enabled */
129 #define IIR_CH 0x0C /* Character timeout*/
130
131 /* equates for FIFO control register */
132
133 #define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */
134 #define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */
135 #define FCR_XMITCLR 0x04 /* clear XMIT FIFO */
136
137 /* equates for Apollo Lake clock control register (PRV_CLOCK_PARAMS) */
138
139 #define PCP_UPDATE 0x80000000 /* update clock */
140 #define PCP_EN 0x00000001 /* enable clock output */
141
142 /* Fields for TI K3 UART module */
143
144 #define MDR1_MODE_SELECT_FIELD_MASK BIT_MASK(3)
145 #define MDR1_MODE_SELECT_FIELD_SHIFT BIT_MASK(0)
146
147 /* Modes available for TI K3 UART module */
148
149 #define MDR1_STD_MODE (0)
150 #define MDR1_SIR_MODE (1)
151 #define MDR1_UART_16X (2)
152 #define MDR1_UART_13X (3)
153 #define MDR1_MIR_MODE (4)
154 #define MDR1_FIR_MODE (5)
155 #define MDR1_CIR_MODE (6)
156 #define MDR1_DISABLE (7)
157
158 /*
159 * Per PC16550D (Literature Number: SNLS378B):
160 *
161 * RXRDY, Mode 0: When in the 16450 Mode (FCR0 = 0) or in
162 * the FIFO Mode (FCR0 = 1, FCR3 = 0) and there is at least 1
163 * character in the RCVR FIFO or RCVR holding register, the
164 * RXRDY pin (29) will be low active. Once it is activated the
165 * RXRDY pin will go inactive when there are no more charac-
166 * ters in the FIFO or holding register.
167 *
168 * RXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when the
169 * FCR3 = 1 and the trigger level or the timeout has been
170 * reached, the RXRDY pin will go low active. Once it is acti-
171 * vated it will go inactive when there are no more characters
172 * in the FIFO or holding register.
173 *
174 * TXRDY, Mode 0: In the 16450 Mode (FCR0 = 0) or in the
175 * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
176 * ters in the XMIT FIFO or XMIT holding register, the TXRDY
177 * pin (24) will be low active. Once it is activated the TXRDY
178 * pin will go inactive after the first character is loaded into the
179 * XMIT FIFO or holding register.
180 *
181 * TXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when
182 * FCR3 = 1 and there are no characters in the XMIT FIFO, the
183 * TXRDY pin will go low active. This pin will become inactive
184 * when the XMIT FIFO is completely full.
185 */
186 #define FCR_MODE0 0x00 /* set receiver in mode 0 */
187 #define FCR_MODE1 0x08 /* set receiver in mode 1 */
188
189 /* RCVR FIFO interrupt levels: trigger interrupt with this bytes in FIFO */
190 #define FCR_FIFO_1 0x00 /* 1 byte in RCVR FIFO */
191 #define FCR_FIFO_4 0x40 /* 4 bytes in RCVR FIFO */
192 #define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */
193 #define FCR_FIFO_14 0xC0 /* 14 bytes in RCVR FIFO */
194
195 /*
196 * UART NS16750 supports 64 bytes FIFO, which can be enabled
197 * via the FCR register
198 */
199 #define FCR_FIFO_64 0x20 /* Enable 64 bytes FIFO */
200
201 /* constants for line control register */
202
203 #define LCR_CS5 0x00 /* 5 bits data size */
204 #define LCR_CS6 0x01 /* 6 bits data size */
205 #define LCR_CS7 0x02 /* 7 bits data size */
206 #define LCR_CS8 0x03 /* 8 bits data size */
207 #define LCR_2_STB 0x04 /* 2 stop bits */
208 #define LCR_1_STB 0x00 /* 1 stop bit */
209 #define LCR_PEN 0x08 /* parity enable */
210 #define LCR_PDIS 0x00 /* parity disable */
211 #define LCR_EPS 0x10 /* even parity select */
212 #define LCR_SP 0x20 /* stick parity select */
213 #define LCR_SBRK 0x40 /* break control bit */
214 #define LCR_DLAB 0x80 /* divisor latch access enable */
215
216 /* constants for the modem control register */
217
218 #define MCR_DTR 0x01 /* dtr output */
219 #define MCR_RTS 0x02 /* rts output */
220 #define MCR_OUT1 0x04 /* output #1 */
221 #define MCR_OUT2 0x08 /* output #2 */
222 #define MCR_LOOP 0x10 /* loop back */
223 #define MCR_AFCE 0x20 /* auto flow control enable */
224
225 /* constants for line status register */
226
227 #define LSR_RXRDY 0x01 /* receiver data available */
228 #define LSR_OE 0x02 /* overrun error */
229 #define LSR_PE 0x04 /* parity error */
230 #define LSR_FE 0x08 /* framing error */
231 #define LSR_BI 0x10 /* break interrupt */
232 #define LSR_EOB_MASK 0x1E /* Error or Break mask */
233 #define LSR_THRE 0x20 /* transmit holding register empty */
234 #define LSR_TEMT 0x40 /* transmitter empty */
235
236 /* constants for modem status register */
237
238 #define MSR_DCTS 0x01 /* cts change */
239 #define MSR_DDSR 0x02 /* dsr change */
240 #define MSR_DRI 0x04 /* ring change */
241 #define MSR_DDCD 0x08 /* data carrier change */
242 #define MSR_CTS 0x10 /* complement of cts */
243 #define MSR_DSR 0x20 /* complement of dsr */
244 #define MSR_RI 0x40 /* complement of ring signal */
245 #define MSR_DCD 0x80 /* complement of dcd */
246
247 #define THR(dev) (get_port(dev) + (REG_THR * reg_interval(dev)))
248 #define RDR(dev) (get_port(dev) + (REG_RDR * reg_interval(dev)))
249 #define BRDL(dev) (get_port(dev) + (REG_BRDL * reg_interval(dev)))
250 #define BRDH(dev) (get_port(dev) + (REG_BRDH * reg_interval(dev)))
251 #define IER(dev) (get_port(dev) + (REG_IER * reg_interval(dev)))
252 #define IIR(dev) (get_port(dev) + (REG_IIR * reg_interval(dev)))
253 #define FCR(dev) (get_port(dev) + (REG_FCR * reg_interval(dev)))
254 #define LCR(dev) (get_port(dev) + (REG_LCR * reg_interval(dev)))
255 #define MDC(dev) (get_port(dev) + (REG_MDC * reg_interval(dev)))
256 #define LSR(dev) (get_port(dev) + (REG_LSR * reg_interval(dev)))
257 #define MSR(dev) (get_port(dev) + (REG_MSR * reg_interval(dev)))
258 #define MDR1(dev) (get_port(dev) + (REG_MDR1 * reg_interval(dev)))
259 #define USR(dev) (get_port(dev) + REG_USR)
260 #define DLF(dev) (get_port(dev) + REG_DLF)
261 #define PCP(dev) (get_port(dev) + REG_PCP)
262
263 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
264 #define SRC_TRAN(dev) (get_port(dev) + REG_LPSS_SRC_TRAN)
265 #define CLR_SRC_TRAN(dev) (get_port(dev) + REG_LPSS_CLR_SRC_TRAN)
266 #define MST(dev) (get_port(dev) + REG_LPSS_MST)
267
268 #define UNMASK_LPSS_INT(chan) (BIT(chan) | (BIT(8) << chan)) /* unmask LPSS DMA Interrupt */
269 #endif
270
271 #define IIRC(dev) (((struct uart_ns16550_dev_data *)(dev)->data)->iir_cache)
272
273 #ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
274 /* Register definitions (ITE_IT8XXX2) */
275 #define REG_ECSPMR 0x08 /* EC Serial port mode reg */
276
277 /* Fields for ITE IT8XXX2 UART module */
278 #define ECSPMR_ECHS 0x02 /* EC high speed select */
279
280 /* IT8XXX2 UART high speed baud rate settings */
281 #define UART_BAUDRATE_115200 115200
282 #define UART_BAUDRATE_230400 230400
283 #define UART_BAUDRATE_460800 460800
284 #define IT8XXX2_230400_DIVISOR 32770
285 #define IT8XXX2_460800_DIVISOR 32769
286
287 #define ECSPMR(dev) (get_port(dev) + REG_ECSPMR * reg_interval(dev))
288 #endif
289
290 #if defined(CONFIG_UART_ASYNC_API)
291 struct uart_ns16550_rx_dma_params {
292 const struct device *dma_dev;
293 uint8_t dma_channel;
294 struct dma_config dma_cfg;
295 struct dma_block_config active_dma_block;
296 uint8_t *buf;
297 size_t buf_len;
298 size_t offset;
299 size_t counter;
300 struct k_work_delayable timeout_work;
301 size_t timeout_us;
302 };
303
304 struct uart_ns16550_tx_dma_params {
305 const struct device *dma_dev;
306 uint8_t dma_channel;
307 struct dma_config dma_cfg;
308 struct dma_block_config active_dma_block;
309 const uint8_t *buf;
310 size_t buf_len;
311 struct k_work_delayable timeout_work;
312 size_t timeout_us;
313 };
314
315 struct uart_ns16550_async_data {
316 const struct device *uart_dev;
317 struct uart_ns16550_tx_dma_params tx_dma_params;
318 struct uart_ns16550_rx_dma_params rx_dma_params;
319 uint8_t *next_rx_buffer;
320 size_t next_rx_buffer_len;
321 uart_callback_t user_callback;
322 void *user_data;
323 };
324
325 static void uart_ns16550_async_rx_timeout(struct k_work *work);
326 static void uart_ns16550_async_tx_timeout(struct k_work *work);
327 #endif
328
329 /** Device config structure */
330 struct uart_ns16550_dev_config {
331 union {
332 DEVICE_MMIO_ROM;
333 uint32_t port;
334 };
335 uint32_t sys_clk_freq;
336 const struct device *clock_dev;
337 clock_control_subsys_t clock_subsys;
338 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
339 uart_irq_config_func_t irq_config_func;
340 #endif
341 #if UART_NS16550_PCP_ENABLED
342 uint32_t pcp;
343 #endif
344 uint8_t reg_interval;
345 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
346 struct pcie_dev *pcie;
347 #endif
348 #if defined(CONFIG_PINCTRL)
349 const struct pinctrl_dev_config *pincfg;
350 #endif
351 #if UART_NS16550_IOPORT_ENABLED
352 bool io_map;
353 #endif
354 #if UART_NS16550_RESET_ENABLED
355 struct reset_dt_spec reset_spec;
356 #endif
357 };
358
359 /** Device data structure */
360 struct uart_ns16550_dev_data {
361 DEVICE_MMIO_RAM;
362 struct uart_config uart_config;
363 struct k_spinlock lock;
364 uint8_t fifo_size;
365
366 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
367 uint8_t iir_cache; /**< cache of IIR since it clears when read */
368 uart_irq_callback_user_data_t cb; /**< Callback function pointer */
369 void *cb_data; /**< Callback function arg */
370 #endif
371
372 #if UART_NS16550_DLF_ENABLED
373 uint8_t dlf; /**< DLF value */
374 #endif
375
376 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
377 bool tx_stream_on;
378 #endif
379
380 #if defined(CONFIG_UART_ASYNC_API)
381 uint64_t phys_addr;
382 struct uart_ns16550_async_data async;
383 #endif
384 };
385
ns16550_outbyte(const struct uart_ns16550_dev_config * cfg,uintptr_t port,uint8_t val)386 static void ns16550_outbyte(const struct uart_ns16550_dev_config *cfg,
387 uintptr_t port, uint8_t val)
388 {
389 #if UART_NS16550_IOPORT_ENABLED
390 if (cfg->io_map) {
391 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
392 sys_out32(val, port);
393 } else {
394 sys_out8(val, port);
395 }
396 } else {
397 #else
398 {
399 #endif
400 /* MMIO mapped */
401 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
402 sys_write32(val, port);
403 } else {
404 sys_write8(val, port);
405 }
406 }
407 }
408
409 static uint8_t ns16550_inbyte(const struct uart_ns16550_dev_config *cfg,
410 uintptr_t port)
411 {
412 #if UART_NS16550_IOPORT_ENABLED
413 if (cfg->io_map) {
414 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
415 return sys_in32(port);
416 } else {
417 return sys_in8(port);
418 }
419 } else {
420 #else
421 {
422 #endif
423 /* MMIO mapped */
424 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
425 return sys_read32(port);
426 } else {
427 return sys_read8(port);
428 }
429 }
430 return 0;
431 }
432
433 __maybe_unused
434 static void ns16550_outword(const struct uart_ns16550_dev_config *cfg,
435 uintptr_t port, uint32_t val)
436 {
437 #if UART_NS16550_IOPORT_ENABLED
438 if (cfg->io_map) {
439 sys_out32(val, port);
440 } else {
441 #else
442 {
443 #endif
444 /* MMIO mapped */
445 sys_write32(val, port);
446 }
447 }
448
449 __maybe_unused
450 static uint32_t ns16550_inword(const struct uart_ns16550_dev_config *cfg,
451 uintptr_t port)
452 {
453 #if UART_NS16550_IOPORT_ENABLED
454 if (cfg->io_map) {
455 return sys_in32(port);
456 }
457 #endif
458 /* MMIO mapped */
459 return sys_read32(port);
460 }
461
462 static inline uint8_t reg_interval(const struct device *dev)
463 {
464 const struct uart_ns16550_dev_config *config = dev->config;
465
466 return config->reg_interval;
467 }
468
469 static inline uintptr_t get_port(const struct device *dev)
470 {
471 uintptr_t port;
472 #if UART_NS16550_IOPORT_ENABLED
473 const struct uart_ns16550_dev_config *config = dev->config;
474
475 if (config->io_map) {
476 port = config->port;
477 } else {
478 #else
479 {
480 #endif
481 port = DEVICE_MMIO_GET(dev);
482 }
483
484 return port;
485 }
486
487 static uint32_t get_uart_baudrate_divisor(const struct device *dev,
488 uint32_t baud_rate,
489 uint32_t pclk)
490 {
491 ARG_UNUSED(dev);
492 /*
493 * calculate baud rate divisor. a variant of
494 * (uint32_t)(pclk / (16.0 * baud_rate) + 0.5)
495 */
496 return ((pclk + (baud_rate << 3)) / baud_rate) >> 4;
497 }
498
499 #ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
500 static uint32_t get_ite_uart_baudrate_divisor(const struct device *dev,
501 uint32_t baud_rate,
502 uint32_t pclk)
503 {
504 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
505 uint32_t divisor = 0;
506
507 if (baud_rate > UART_BAUDRATE_115200) {
508 /* Baud rate divisor for high speed */
509 if (baud_rate == UART_BAUDRATE_230400) {
510 divisor = IT8XXX2_230400_DIVISOR;
511 } else if (baud_rate == UART_BAUDRATE_460800) {
512 divisor = IT8XXX2_460800_DIVISOR;
513 }
514 /*
515 * This bit indicates that the supported baud rate of
516 * UART1/UART2 can be up to 230.4k and 460.8k.
517 * Other bits are reserved and have no setting, so we
518 * directly write the ECSPMR register.
519 */
520 ns16550_outbyte(dev_cfg, ECSPMR(dev), ECSPMR_ECHS);
521 } else {
522 divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
523 /* Set ECSPMR register as default */
524 ns16550_outbyte(dev_cfg, ECSPMR(dev), 0);
525 }
526
527 return divisor;
528 }
529 #endif
530
531 static inline int ns16550_read_char(const struct device *dev, unsigned char *c)
532 {
533 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
534
535 if ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_RXRDY) != 0) {
536 *c = ns16550_inbyte(dev_cfg, RDR(dev));
537 return 0;
538 }
539
540 return -1;
541 }
542
543 static void set_baud_rate(const struct device *dev, uint32_t baud_rate, uint32_t pclk)
544 {
545 struct uart_ns16550_dev_data * const dev_data = dev->data;
546 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
547 uint32_t divisor; /* baud rate divisor */
548 uint8_t lcr_cache;
549
550 if ((baud_rate != 0U) && (pclk != 0U)) {
551 #ifdef CONFIG_UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
552 divisor = get_ite_uart_baudrate_divisor(dev, baud_rate, pclk);
553 #else
554 divisor = get_uart_baudrate_divisor(dev, baud_rate, pclk);
555 #endif
556 /* set the DLAB to access the baud rate divisor registers */
557 lcr_cache = ns16550_inbyte(dev_cfg, LCR(dev));
558 ns16550_outbyte(dev_cfg, LCR(dev), LCR_DLAB | lcr_cache);
559 ns16550_outbyte(dev_cfg, BRDL(dev), (unsigned char)(divisor & 0xff));
560 ns16550_outbyte(dev_cfg, BRDH(dev), (unsigned char)((divisor >> 8) & 0xff));
561
562 /* restore the DLAB to access the baud rate divisor registers */
563 ns16550_outbyte(dev_cfg, LCR(dev), lcr_cache);
564
565 dev_data->uart_config.baudrate = baud_rate;
566 }
567 }
568
569 static int uart_ns16550_configure(const struct device *dev,
570 const struct uart_config *cfg)
571 {
572 struct uart_ns16550_dev_data * const dev_data = dev->data;
573 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
574 uint8_t mdc = 0U, c;
575 uint32_t pclk = 0U;
576
577 /* temp for return value if error occurs in this locked region */
578 int ret = 0;
579
580 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
581
582 #if defined(CONFIG_PINCTRL)
583 if (dev_cfg->pincfg != NULL) {
584 pinctrl_apply_state(dev_cfg->pincfg, PINCTRL_STATE_DEFAULT);
585 }
586 #endif
587
588 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
589 dev_data->iir_cache = 0U;
590 #endif
591
592 #if UART_NS16550_DLF_ENABLED
593 ns16550_outbyte(dev_cfg, DLF(dev), dev_data->dlf);
594 #endif
595
596 #if UART_NS16550_PCP_ENABLED
597 uint32_t pcp = dev_cfg->pcp;
598
599 if (pcp) {
600 pcp |= PCP_EN;
601 ns16550_outbyte(dev_cfg, PCP(dev), pcp & ~PCP_UPDATE);
602 ns16550_outbyte(dev_cfg, PCP(dev), pcp | PCP_UPDATE);
603 }
604 #endif
605
606 #ifdef CONFIG_UART_NS16550_TI_K3
607 uint32_t mdr = ns16550_inbyte(dev_cfg, MDR1(dev));
608
609 mdr = ((mdr & ~MDR1_MODE_SELECT_FIELD_MASK) | ((((MDR1_STD_MODE) <<
610 MDR1_MODE_SELECT_FIELD_SHIFT)) & MDR1_MODE_SELECT_FIELD_MASK));
611 ns16550_outbyte(dev_cfg, MDR1(dev), mdr);
612 #endif
613 /*
614 * set clock frequency from clock_frequency property if valid,
615 * otherwise, get clock frequency from clock manager
616 */
617 if (dev_cfg->sys_clk_freq != 0U) {
618 pclk = dev_cfg->sys_clk_freq;
619 } else {
620 if (!device_is_ready(dev_cfg->clock_dev)) {
621 ret = -EINVAL;
622 goto out;
623 }
624
625 if (clock_control_get_rate(dev_cfg->clock_dev,
626 dev_cfg->clock_subsys,
627 &pclk) != 0) {
628 ret = -EINVAL;
629 goto out;
630 }
631 }
632
633 set_baud_rate(dev, cfg->baudrate, pclk);
634
635 /* Local structure to hold temporary values to pass to ns16550_outbyte() */
636 struct uart_config uart_cfg;
637
638 switch (cfg->data_bits) {
639 case UART_CFG_DATA_BITS_5:
640 uart_cfg.data_bits = LCR_CS5;
641 break;
642 case UART_CFG_DATA_BITS_6:
643 uart_cfg.data_bits = LCR_CS6;
644 break;
645 case UART_CFG_DATA_BITS_7:
646 uart_cfg.data_bits = LCR_CS7;
647 break;
648 case UART_CFG_DATA_BITS_8:
649 uart_cfg.data_bits = LCR_CS8;
650 break;
651 default:
652 ret = -ENOTSUP;
653 goto out;
654 }
655
656 switch (cfg->stop_bits) {
657 case UART_CFG_STOP_BITS_1:
658 uart_cfg.stop_bits = LCR_1_STB;
659 break;
660 case UART_CFG_STOP_BITS_2:
661 uart_cfg.stop_bits = LCR_2_STB;
662 break;
663 default:
664 ret = -ENOTSUP;
665 goto out;
666 }
667
668 switch (cfg->parity) {
669 case UART_CFG_PARITY_NONE:
670 uart_cfg.parity = LCR_PDIS;
671 break;
672 case UART_CFG_PARITY_EVEN:
673 uart_cfg.parity = LCR_EPS;
674 break;
675 default:
676 ret = -ENOTSUP;
677 goto out;
678 }
679
680 dev_data->uart_config = *cfg;
681
682 /* data bits, stop bits, parity, clear DLAB */
683 ns16550_outbyte(dev_cfg, LCR(dev),
684 uart_cfg.data_bits | uart_cfg.stop_bits | uart_cfg.parity);
685
686 mdc = MCR_OUT2 | MCR_RTS | MCR_DTR;
687 #if defined(CONFIG_UART_NS16550_VARIANT_NS16750) || \
688 defined(CONFIG_UART_NS16550_VARIANT_NS16950)
689 if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS) {
690 mdc |= MCR_AFCE;
691 }
692 #endif
693
694 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
695
696 /*
697 * Program FIFO: enabled, mode 0 (set for compatibility with quark),
698 * generate the interrupt at 8th byte
699 * Clear TX and RX FIFO
700 */
701 ns16550_outbyte(dev_cfg, FCR(dev),
702 FCR_FIFO | FCR_MODE0 | FCR_FIFO_8 | FCR_RCVRCLR | FCR_XMITCLR
703 #ifdef CONFIG_UART_NS16550_VARIANT_NS16750
704 | FCR_FIFO_64
705 #endif
706 );
707
708 if ((ns16550_inbyte(dev_cfg, IIR(dev)) & IIR_FE) == IIR_FE) {
709 #ifdef CONFIG_UART_NS16550_VARIANT_NS16750
710 dev_data->fifo_size = 64;
711 #elif defined(CONFIG_UART_NS16550_VARIANT_NS16950)
712 dev_data->fifo_size = 128;
713 #else
714 dev_data->fifo_size = 16;
715 #endif
716 } else {
717 dev_data->fifo_size = 1;
718 }
719
720 /* clear the port */
721 (void)ns16550_read_char(dev, &c);
722
723 /* disable interrupts */
724 ns16550_outbyte(dev_cfg, IER(dev), 0x00);
725
726 out:
727 k_spin_unlock(&dev_data->lock, key);
728 return ret;
729 };
730
731 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
732 static int uart_ns16550_config_get(const struct device *dev,
733 struct uart_config *cfg)
734 {
735 struct uart_ns16550_dev_data *data = dev->data;
736
737 cfg->baudrate = data->uart_config.baudrate;
738 cfg->parity = data->uart_config.parity;
739 cfg->stop_bits = data->uart_config.stop_bits;
740 cfg->data_bits = data->uart_config.data_bits;
741 cfg->flow_ctrl = data->uart_config.flow_ctrl;
742
743 return 0;
744 }
745 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
746
747 #if UART_NS16550_RESET_ENABLED
748 /**
749 * @brief Toggle the reset UART line
750 *
751 * This routine is called to bring UART IP out of reset state.
752 *
753 * @param reset_spec Reset controller device configuration struct
754 *
755 * @return 0 if successful, failed otherwise
756 */
757 static int uart_reset_config(const struct reset_dt_spec *reset_spec)
758 {
759 int ret;
760
761 if (!device_is_ready(reset_spec->dev)) {
762 LOG_ERR("Reset controller device is not ready");
763 return -ENODEV;
764 }
765
766 ret = reset_line_toggle(reset_spec->dev, reset_spec->id);
767 if (ret != 0) {
768 LOG_ERR("UART toggle reset line failed");
769 return ret;
770 }
771
772 return 0;
773 }
774 #endif /* UART_NS16550_RESET_ENABLED */
775
776 #if (IS_ENABLED(CONFIG_UART_ASYNC_API))
777 static inline void async_timer_start(struct k_work_delayable *work, size_t timeout_us)
778 {
779 if ((timeout_us != SYS_FOREVER_US) && (timeout_us != 0)) {
780 k_work_reschedule(work, K_USEC(timeout_us));
781 }
782 }
783
784 #endif
785
786 /**
787 * @brief Initialize individual UART port
788 *
789 * This routine is called to reset the chip in a quiescent state.
790 *
791 * @param dev UART device struct
792 *
793 * @return 0 if successful, failed otherwise
794 */
795 static int uart_ns16550_init(const struct device *dev)
796 {
797 struct uart_ns16550_dev_data *data = dev->data;
798 const struct uart_ns16550_dev_config *dev_cfg = dev->config;
799 int ret;
800
801 ARG_UNUSED(dev_cfg);
802
803 #if UART_NS16550_RESET_ENABLED
804 /* Assert the UART reset line if it is defined. */
805 if (dev_cfg->reset_spec.dev != NULL) {
806 ret = uart_reset_config(&(dev_cfg->reset_spec));
807 if (ret != 0) {
808 return ret;
809 }
810 }
811 #endif
812
813 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
814 if (dev_cfg->pcie) {
815 struct pcie_bar mbar;
816
817 if (dev_cfg->pcie->bdf == PCIE_BDF_NONE) {
818 return -EINVAL;
819 }
820
821 pcie_probe_mbar(dev_cfg->pcie->bdf, 0, &mbar);
822 pcie_set_cmd(dev_cfg->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true);
823
824 device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size,
825 K_MEM_CACHE_NONE);
826 #if defined(CONFIG_UART_ASYNC_API)
827 if (data->async.tx_dma_params.dma_dev != NULL) {
828 pcie_set_cmd(dev_cfg->pcie->bdf, PCIE_CONF_CMDSTAT_MASTER, true);
829 data->phys_addr = mbar.phys_addr;
830 }
831 #endif
832 } else
833 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) */
834 {
835 #if UART_NS16550_IOPORT_ENABLED
836 /* Map directly from DTS */
837 if (!dev_cfg->io_map) {
838 #else
839 {
840 #endif
841 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
842 }
843 }
844 #if defined(CONFIG_UART_ASYNC_API)
845 if (data->async.tx_dma_params.dma_dev != NULL) {
846 data->async.next_rx_buffer = NULL;
847 data->async.next_rx_buffer_len = 0;
848 data->async.uart_dev = dev;
849 k_work_init_delayable(&data->async.rx_dma_params.timeout_work,
850 uart_ns16550_async_rx_timeout);
851 k_work_init_delayable(&data->async.tx_dma_params.timeout_work,
852 uart_ns16550_async_tx_timeout);
853 data->async.rx_dma_params.dma_cfg.head_block =
854 &data->async.rx_dma_params.active_dma_block;
855 data->async.tx_dma_params.dma_cfg.head_block =
856 &data->async.tx_dma_params.active_dma_block;
857 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
858 #if UART_NS16550_IOPORT_ENABLED
859 if (!dev_cfg->io_map)
860 #endif
861 {
862 uintptr_t base;
863
864 base = DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET;
865 dma_intel_lpss_set_base(data->async.tx_dma_params.dma_dev, base);
866 dma_intel_lpss_setup(data->async.tx_dma_params.dma_dev);
867 sys_write32((uint32_t)data->phys_addr,
868 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_LOW);
869 sys_write32((uint32_t)(data->phys_addr >> DMA_INTEL_LPSS_ADDR_RIGHT_SHIFT),
870 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_HI);
871 }
872 #endif
873 }
874 #endif
875 ret = uart_ns16550_configure(dev, &data->uart_config);
876 if (ret != 0) {
877 return ret;
878 }
879
880 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
881 dev_cfg->irq_config_func(dev);
882 #endif
883
884 return 0;
885 }
886
887 /**
888 * @brief Poll the device for input.
889 *
890 * @param dev UART device struct
891 * @param c Pointer to character
892 *
893 * @return 0 if a character arrived, -1 if the input buffer if empty.
894 */
895 static int uart_ns16550_poll_in(const struct device *dev, unsigned char *c)
896 {
897 struct uart_ns16550_dev_data *data = dev->data;
898 int ret = -1;
899 k_spinlock_key_t key = k_spin_lock(&data->lock);
900
901 ret = ns16550_read_char(dev, c);
902
903 k_spin_unlock(&data->lock, key);
904
905 return ret;
906 }
907
908 /**
909 * @brief Output a character in polled mode.
910 *
911 * Checks if the transmitter is empty. If empty, a character is written to
912 * the data register.
913 *
914 * If the hardware flow control is enabled then the handshake signal CTS has to
915 * be asserted in order to send a character.
916 *
917 * @param dev UART device struct
918 * @param c Character to send
919 */
920 static void uart_ns16550_poll_out(const struct device *dev,
921 unsigned char c)
922 {
923 struct uart_ns16550_dev_data *data = dev->data;
924 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
925 k_spinlock_key_t key = k_spin_lock(&data->lock);
926
927 while ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_THRE) == 0) {
928 }
929
930 ns16550_outbyte(dev_cfg, THR(dev), c);
931
932 k_spin_unlock(&data->lock, key);
933 }
934
935 /**
936 * @brief Check if an error was received
937 *
938 * @param dev UART device struct
939 *
940 * @return one of UART_ERROR_OVERRUN, UART_ERROR_PARITY, UART_ERROR_FRAMING,
941 * UART_BREAK if an error was detected, 0 otherwise.
942 */
943 static int uart_ns16550_err_check(const struct device *dev)
944 {
945 struct uart_ns16550_dev_data *data = dev->data;
946 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
947 k_spinlock_key_t key = k_spin_lock(&data->lock);
948 int check = (ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_EOB_MASK);
949
950 k_spin_unlock(&data->lock, key);
951
952 return check >> 1;
953 }
954
955 #if CONFIG_UART_INTERRUPT_DRIVEN
956
957 /**
958 * @brief Fill FIFO with data
959 *
960 * @param dev UART device struct
961 * @param tx_data Data to transmit
962 * @param size Number of bytes to send
963 *
964 * @return Number of bytes sent
965 */
966 static int uart_ns16550_fifo_fill(const struct device *dev,
967 const uint8_t *tx_data,
968 int size)
969 {
970 struct uart_ns16550_dev_data *data = dev->data;
971 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
972 int i;
973 k_spinlock_key_t key = k_spin_lock(&data->lock);
974
975 for (i = 0; (i < size) && (i < data->fifo_size); i++) {
976 ns16550_outbyte(dev_cfg, THR(dev), tx_data[i]);
977 }
978
979 k_spin_unlock(&data->lock, key);
980
981 return i;
982 }
983
984 /**
985 * @brief Read data from FIFO
986 *
987 * @param dev UART device struct
988 * @param rxData Data container
989 * @param size Container size
990 *
991 * @return Number of bytes read
992 */
993 static int uart_ns16550_fifo_read(const struct device *dev, uint8_t *rx_data,
994 const int size)
995 {
996 struct uart_ns16550_dev_data *data = dev->data;
997 int i;
998 k_spinlock_key_t key = k_spin_lock(&data->lock);
999
1000 for (i = 0; (i < size) && (ns16550_read_char(dev, &rx_data[i]) != -1); i++) {
1001 }
1002
1003 k_spin_unlock(&data->lock, key);
1004
1005 return i;
1006 }
1007
1008 /**
1009 * @brief Enable TX interrupt in IER
1010 *
1011 * @param dev UART device struct
1012 */
1013 static void uart_ns16550_irq_tx_enable(const struct device *dev)
1014 {
1015 struct uart_ns16550_dev_data *data = dev->data;
1016 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1017 k_spinlock_key_t key = k_spin_lock(&data->lock);
1018
1019 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
1020 struct uart_ns16550_dev_data *const dev_data = dev->data;
1021
1022 if (!dev_data->tx_stream_on) {
1023 dev_data->tx_stream_on = true;
1024 uint8_t num_cpu_states;
1025 const struct pm_state_info *cpu_states;
1026
1027 num_cpu_states = pm_state_cpu_get_all(0U, &cpu_states);
1028
1029 /*
1030 * Power state to be disabled. Some platforms have multiple
1031 * states and need to be given a constraint set according to
1032 * different states.
1033 */
1034 for (uint8_t i = 0U; i < num_cpu_states; i++) {
1035 pm_policy_state_lock_get(cpu_states[i].state, PM_ALL_SUBSTATES);
1036 }
1037 }
1038 #endif
1039 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_TBE);
1040
1041 k_spin_unlock(&data->lock, key);
1042 }
1043
1044 /**
1045 * @brief Disable TX interrupt in IER
1046 *
1047 * @param dev UART device struct
1048 */
1049 static void uart_ns16550_irq_tx_disable(const struct device *dev)
1050 {
1051 struct uart_ns16550_dev_data *data = dev->data;
1052 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1053 k_spinlock_key_t key = k_spin_lock(&data->lock);
1054
1055 ns16550_outbyte(dev_cfg, IER(dev),
1056 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_TBE));
1057
1058 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
1059 struct uart_ns16550_dev_data *const dev_data = dev->data;
1060
1061 if (dev_data->tx_stream_on) {
1062 dev_data->tx_stream_on = false;
1063 uint8_t num_cpu_states;
1064 const struct pm_state_info *cpu_states;
1065
1066 num_cpu_states = pm_state_cpu_get_all(0U, &cpu_states);
1067
1068 /*
1069 * Power state to be enabled. Some platforms have multiple
1070 * states and need to be given a constraint release according
1071 * to different states.
1072 */
1073 for (uint8_t i = 0U; i < num_cpu_states; i++) {
1074 pm_policy_state_lock_put(cpu_states[i].state, PM_ALL_SUBSTATES);
1075 }
1076 }
1077 #endif
1078 k_spin_unlock(&data->lock, key);
1079 }
1080
1081 /**
1082 * @brief Check if Tx IRQ has been raised
1083 *
1084 * @param dev UART device struct
1085 *
1086 * @return 1 if an IRQ is ready, 0 otherwise
1087 */
1088 static int uart_ns16550_irq_tx_ready(const struct device *dev)
1089 {
1090 struct uart_ns16550_dev_data *data = dev->data;
1091 k_spinlock_key_t key = k_spin_lock(&data->lock);
1092
1093 int ret = ((IIRC(dev) & IIR_ID) == IIR_THRE) ? 1 : 0;
1094
1095 k_spin_unlock(&data->lock, key);
1096
1097 return ret;
1098 }
1099
1100 /**
1101 * @brief Check if nothing remains to be transmitted
1102 *
1103 * @param dev UART device struct
1104 *
1105 * @return 1 if nothing remains to be transmitted, 0 otherwise
1106 */
1107 static int uart_ns16550_irq_tx_complete(const struct device *dev)
1108 {
1109 struct uart_ns16550_dev_data *data = dev->data;
1110 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1111 k_spinlock_key_t key = k_spin_lock(&data->lock);
1112
1113 int ret = ((ns16550_inbyte(dev_cfg, LSR(dev)) & (LSR_TEMT | LSR_THRE))
1114 == (LSR_TEMT | LSR_THRE)) ? 1 : 0;
1115
1116 k_spin_unlock(&data->lock, key);
1117
1118 return ret;
1119 }
1120
1121 /**
1122 * @brief Enable RX interrupt in IER
1123 *
1124 * @param dev UART device struct
1125 */
1126 static void uart_ns16550_irq_rx_enable(const struct device *dev)
1127 {
1128 struct uart_ns16550_dev_data *data = dev->data;
1129 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1130 k_spinlock_key_t key = k_spin_lock(&data->lock);
1131
1132 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_RXRDY);
1133
1134 k_spin_unlock(&data->lock, key);
1135 }
1136
1137 /**
1138 * @brief Disable RX interrupt in IER
1139 *
1140 * @param dev UART device struct
1141 */
1142 static void uart_ns16550_irq_rx_disable(const struct device *dev)
1143 {
1144 struct uart_ns16550_dev_data *data = dev->data;
1145 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1146 k_spinlock_key_t key = k_spin_lock(&data->lock);
1147
1148 ns16550_outbyte(dev_cfg, IER(dev),
1149 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_RXRDY));
1150
1151 k_spin_unlock(&data->lock, key);
1152 }
1153
1154 /**
1155 * @brief Check if Rx IRQ has been raised
1156 *
1157 * @param dev UART device struct
1158 *
1159 * @return 1 if an IRQ is ready, 0 otherwise
1160 */
1161 static int uart_ns16550_irq_rx_ready(const struct device *dev)
1162 {
1163 struct uart_ns16550_dev_data *data = dev->data;
1164 k_spinlock_key_t key = k_spin_lock(&data->lock);
1165
1166 int ret = ((IIRC(dev) & IIR_ID) == IIR_RBRF) ? 1 : 0;
1167
1168 k_spin_unlock(&data->lock, key);
1169
1170 return ret;
1171 }
1172
1173 /**
1174 * @brief Enable error interrupt in IER
1175 *
1176 * @param dev UART device struct
1177 */
1178 static void uart_ns16550_irq_err_enable(const struct device *dev)
1179 {
1180 struct uart_ns16550_dev_data *data = dev->data;
1181 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1182 k_spinlock_key_t key = k_spin_lock(&data->lock);
1183
1184 ns16550_outbyte(dev_cfg, IER(dev),
1185 ns16550_inbyte(dev_cfg, IER(dev)) | IER_LSR);
1186
1187 k_spin_unlock(&data->lock, key);
1188 }
1189
1190 /**
1191 * @brief Disable error interrupt in IER
1192 *
1193 * @param dev UART device struct
1194 *
1195 * @return 1 if an IRQ is ready, 0 otherwise
1196 */
1197 static void uart_ns16550_irq_err_disable(const struct device *dev)
1198 {
1199 struct uart_ns16550_dev_data *data = dev->data;
1200 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1201 k_spinlock_key_t key = k_spin_lock(&data->lock);
1202
1203 ns16550_outbyte(dev_cfg, IER(dev),
1204 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_LSR));
1205
1206 k_spin_unlock(&data->lock, key);
1207 }
1208
1209 /**
1210 * @brief Check if any IRQ is pending
1211 *
1212 * @param dev UART device struct
1213 *
1214 * @return 1 if an IRQ is pending, 0 otherwise
1215 */
1216 static int uart_ns16550_irq_is_pending(const struct device *dev)
1217 {
1218 struct uart_ns16550_dev_data *data = dev->data;
1219 k_spinlock_key_t key = k_spin_lock(&data->lock);
1220
1221 int ret = (!(IIRC(dev) & IIR_NIP)) ? 1 : 0;
1222
1223 k_spin_unlock(&data->lock, key);
1224
1225 return ret;
1226 }
1227
1228 /**
1229 * @brief Update cached contents of IIR
1230 *
1231 * @param dev UART device struct
1232 *
1233 * @return Always 1
1234 */
1235 static int uart_ns16550_irq_update(const struct device *dev)
1236 {
1237 struct uart_ns16550_dev_data *data = dev->data;
1238 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1239 k_spinlock_key_t key = k_spin_lock(&data->lock);
1240
1241 IIRC(dev) = ns16550_inbyte(dev_cfg, IIR(dev));
1242
1243 k_spin_unlock(&data->lock, key);
1244
1245 return 1;
1246 }
1247
1248 /**
1249 * @brief Set the callback function pointer for IRQ.
1250 *
1251 * @param dev UART device struct
1252 * @param cb Callback function pointer.
1253 */
1254 static void uart_ns16550_irq_callback_set(const struct device *dev,
1255 uart_irq_callback_user_data_t cb,
1256 void *cb_data)
1257 {
1258 struct uart_ns16550_dev_data * const dev_data = dev->data;
1259 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
1260
1261 dev_data->cb = cb;
1262 dev_data->cb_data = cb_data;
1263
1264 k_spin_unlock(&dev_data->lock, key);
1265 }
1266
1267 /**
1268 * @brief Interrupt service routine.
1269 *
1270 * This simply calls the callback function, if one exists.
1271 *
1272 * @param arg Argument to ISR.
1273 */
1274 static void uart_ns16550_isr(const struct device *dev)
1275 {
1276 struct uart_ns16550_dev_data * const dev_data = dev->data;
1277 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1278
1279 if (dev_data->cb) {
1280 dev_data->cb(dev, dev_data->cb_data);
1281 } else if ((IS_ENABLED(CONFIG_UART_NS16550_DW8250_DW_APB)) &&
1282 ((ns16550_inbyte(dev_cfg, IIR(dev)) & IIR_MASK) == IIR_BUSY)) {
1283 /*
1284 * The Synopsys DesignWare 8250 has an extra feature whereby
1285 * it detects if the LCR is written whilst busy.
1286 * If it is, then a busy detect interrupt is raised,
1287 * the uart status register need to be read.
1288 */
1289 ns16550_inword(dev_cfg, USR(dev));
1290 }
1291
1292 #if (IS_ENABLED(CONFIG_UART_ASYNC_API))
1293 if (dev_data->async.tx_dma_params.dma_dev != NULL) {
1294 const struct uart_ns16550_dev_config * const config = dev->config;
1295 uint8_t IIR_status = ns16550_inbyte(config, IIR(dev));
1296 #if (IS_ENABLED(CONFIG_UART_NS16550_INTEL_LPSS_DMA))
1297 uint32_t dma_status = ns16550_inword(config, SRC_TRAN(dev));
1298
1299 if (dma_status & BIT(dev_data->async.rx_dma_params.dma_channel)) {
1300 async_timer_start(&dev_data->async.rx_dma_params.timeout_work,
1301 dev_data->async.rx_dma_params.timeout_us);
1302 ns16550_outword(config, CLR_SRC_TRAN(dev),
1303 BIT(dev_data->async.rx_dma_params.dma_channel));
1304 return;
1305 }
1306 dma_intel_lpss_isr(dev_data->async.rx_dma_params.dma_dev);
1307 #endif
1308 if (IIR_status & IIR_RBRF) {
1309 async_timer_start(&dev_data->async.rx_dma_params.timeout_work,
1310 dev_data->async.rx_dma_params.timeout_us);
1311 return;
1312 }
1313 }
1314 #endif
1315
1316 #ifdef CONFIG_UART_NS16550_WA_ISR_REENABLE_INTERRUPT
1317 uint8_t cached_ier = ns16550_inbyte(dev_cfg, IER(dev));
1318
1319 ns16550_outbyte(dev_cfg, IER(dev), 0U);
1320 ns16550_outbyte(dev_cfg, IER(dev), cached_ier);
1321 #endif
1322 }
1323
1324 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1325
1326 #ifdef CONFIG_UART_NS16550_LINE_CTRL
1327
1328 /**
1329 * @brief Manipulate line control for UART.
1330 *
1331 * @param dev UART device struct
1332 * @param ctrl The line control to be manipulated
1333 * @param val Value to set the line control
1334 *
1335 * @return 0 if successful, failed otherwise
1336 */
1337 static int uart_ns16550_line_ctrl_set(const struct device *dev,
1338 uint32_t ctrl, uint32_t val)
1339 {
1340 struct uart_ns16550_dev_data *data = dev->data;
1341 const struct uart_ns16550_dev_config *const dev_cfg = dev->config;
1342 uint32_t mdc, chg, pclk = 0U;
1343 k_spinlock_key_t key;
1344
1345 if (dev_cfg->sys_clk_freq != 0U) {
1346 pclk = dev_cfg->sys_clk_freq;
1347 } else {
1348 if (device_is_ready(dev_cfg->clock_dev)) {
1349 clock_control_get_rate(dev_cfg->clock_dev, dev_cfg->clock_subsys, &pclk);
1350 }
1351 }
1352
1353 switch (ctrl) {
1354 case UART_LINE_CTRL_BAUD_RATE:
1355 set_baud_rate(dev, val, pclk);
1356 return 0;
1357
1358 case UART_LINE_CTRL_RTS:
1359 case UART_LINE_CTRL_DTR:
1360 key = k_spin_lock(&data->lock);
1361 mdc = ns16550_inbyte(dev_cfg, MDC(dev));
1362
1363 if (ctrl == UART_LINE_CTRL_RTS) {
1364 chg = MCR_RTS;
1365 } else {
1366 chg = MCR_DTR;
1367 }
1368
1369 if (val) {
1370 mdc |= chg;
1371 } else {
1372 mdc &= ~(chg);
1373 }
1374 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
1375 k_spin_unlock(&data->lock, key);
1376 return 0;
1377 }
1378
1379 return -ENOTSUP;
1380 }
1381
1382 #endif /* CONFIG_UART_NS16550_LINE_CTRL */
1383
1384 #ifdef CONFIG_UART_NS16550_DRV_CMD
1385
1386 /**
1387 * @brief Send extra command to driver
1388 *
1389 * @param dev UART device struct
1390 * @param cmd Command to driver
1391 * @param p Parameter to the command
1392 *
1393 * @return 0 if successful, failed otherwise
1394 */
1395 static int uart_ns16550_drv_cmd(const struct device *dev, uint32_t cmd,
1396 uint32_t p)
1397 {
1398 #if UART_NS16550_DLF_ENABLED
1399 if (cmd == CMD_SET_DLF) {
1400 struct uart_ns16550_dev_data * const dev_data = dev->data;
1401 const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
1402 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
1403
1404 dev_data->dlf = p;
1405 ns16550_outbyte(dev_cfg, DLF(dev), dev_data->dlf);
1406 k_spin_unlock(&dev_data->lock, key);
1407 return 0;
1408 }
1409 #endif
1410
1411 return -ENOTSUP;
1412 }
1413
1414 #endif /* CONFIG_UART_NS16550_DRV_CMD */
1415
1416 #if (IS_ENABLED(CONFIG_UART_ASYNC_API))
1417 static void async_user_callback(const struct device *dev, struct uart_event *evt)
1418 {
1419 const struct uart_ns16550_dev_data *data = dev->data;
1420
1421 if (data->async.user_callback) {
1422 data->async.user_callback(dev, evt, data->async.user_data);
1423 }
1424 }
1425
1426 #if UART_NS16550_DMAS_ENABLED
1427 static void async_evt_tx_done(struct device *dev)
1428 {
1429 struct uart_ns16550_dev_data *data = dev->data;
1430 struct uart_ns16550_tx_dma_params *tx_params = &data->async.tx_dma_params;
1431
1432 (void)k_work_cancel_delayable(&data->async.tx_dma_params.timeout_work);
1433
1434 struct uart_event event = {
1435 .type = UART_TX_DONE,
1436 .data.tx.buf = tx_params->buf,
1437 .data.tx.len = tx_params->buf_len
1438 };
1439
1440 tx_params->buf = NULL;
1441 tx_params->buf_len = 0U;
1442
1443 async_user_callback(dev, &event);
1444 }
1445 #endif
1446
1447 static void async_evt_rx_rdy(const struct device *dev)
1448 {
1449 struct uart_ns16550_dev_data *data = dev->data;
1450 struct uart_ns16550_rx_dma_params *dma_params = &data->async.rx_dma_params;
1451
1452 struct uart_event event = {
1453 .type = UART_RX_RDY,
1454 .data.rx.buf = dma_params->buf,
1455 .data.rx.len = dma_params->counter - dma_params->offset,
1456 .data.rx.offset = dma_params->offset
1457 };
1458
1459 dma_params->offset = dma_params->counter;
1460
1461 if (event.data.rx.len > 0) {
1462 async_user_callback(dev, &event);
1463 }
1464 }
1465
1466 static void async_evt_rx_buf_release(const struct device *dev)
1467 {
1468 struct uart_ns16550_dev_data *data = (struct uart_ns16550_dev_data *)dev->data;
1469 struct uart_event evt = {
1470 .type = UART_RX_BUF_RELEASED,
1471 .data.rx_buf.buf = data->async.rx_dma_params.buf
1472 };
1473
1474 async_user_callback(dev, &evt);
1475 data->async.rx_dma_params.buf = NULL;
1476 data->async.rx_dma_params.buf_len = 0U;
1477 data->async.rx_dma_params.offset = 0U;
1478 data->async.rx_dma_params.counter = 0U;
1479 }
1480
1481 static void async_evt_rx_buf_request(const struct device *dev)
1482 {
1483 struct uart_event evt = {
1484 .type = UART_RX_BUF_REQUEST
1485 };
1486 async_user_callback(dev, &evt);
1487 }
1488
1489 static void uart_ns16550_async_rx_flush(const struct device *dev)
1490 {
1491 struct uart_ns16550_dev_data *data = dev->data;
1492 struct uart_ns16550_rx_dma_params *dma_params = &data->async.rx_dma_params;
1493 struct dma_status status;
1494
1495 dma_get_status(dma_params->dma_dev,
1496 dma_params->dma_channel,
1497 &status);
1498
1499 const int rx_count = dma_params->buf_len - status.pending_length;
1500
1501 if (rx_count > dma_params->counter) {
1502 dma_params->counter = rx_count;
1503 async_evt_rx_rdy(dev);
1504 }
1505 }
1506
1507 static int uart_ns16550_rx_disable(const struct device *dev)
1508 {
1509 struct uart_ns16550_dev_data *data = (struct uart_ns16550_dev_data *)dev->data;
1510 struct uart_ns16550_rx_dma_params *dma_params = &data->async.rx_dma_params;
1511 k_spinlock_key_t key = k_spin_lock(&data->lock);
1512 int ret = 0;
1513
1514 if (!device_is_ready(dma_params->dma_dev)) {
1515 ret = -ENODEV;
1516 goto out;
1517 }
1518
1519 (void)k_work_cancel_delayable(&data->async.rx_dma_params.timeout_work);
1520
1521 if (dma_params->buf && (dma_params->buf_len > 0)) {
1522 uart_ns16550_async_rx_flush(dev);
1523 async_evt_rx_buf_release(dev);
1524 if (data->async.next_rx_buffer != NULL) {
1525 dma_params->buf = data->async.next_rx_buffer;
1526 dma_params->buf_len = data->async.next_rx_buffer_len;
1527 data->async.next_rx_buffer = NULL;
1528 data->async.next_rx_buffer_len = 0;
1529 async_evt_rx_buf_release(dev);
1530 }
1531 }
1532 ret = dma_stop(dma_params->dma_dev,
1533 dma_params->dma_channel);
1534
1535 struct uart_event event = {
1536 .type = UART_RX_DISABLED
1537 };
1538
1539 async_user_callback(dev, &event);
1540
1541 out:
1542 k_spin_unlock(&data->lock, key);
1543 return ret;
1544 }
1545
1546 static void prepare_rx_dma_block_config(const struct device *dev)
1547 {
1548 struct uart_ns16550_dev_data *data = (struct uart_ns16550_dev_data *)dev->data;
1549 struct uart_ns16550_rx_dma_params *rx_dma_params = &data->async.rx_dma_params;
1550
1551 assert(rx_dma_params->buf != NULL);
1552 assert(rx_dma_params->buf_len > 0);
1553
1554 struct dma_block_config *head_block_config = &rx_dma_params->active_dma_block;
1555
1556 head_block_config->dest_address = (uintptr_t)rx_dma_params->buf;
1557 head_block_config->source_address = data->phys_addr;
1558 head_block_config->block_size = rx_dma_params->buf_len;
1559 }
1560
1561 #if UART_NS16550_DMAS_ENABLED
1562 static void dma_callback(const struct device *dev, void *user_data, uint32_t channel,
1563 int status)
1564 {
1565 struct device *uart_dev = (struct device *)user_data;
1566 struct uart_ns16550_dev_data *data = (struct uart_ns16550_dev_data *)uart_dev->data;
1567 struct uart_ns16550_rx_dma_params *rx_params = &data->async.rx_dma_params;
1568 struct uart_ns16550_tx_dma_params *tx_params = &data->async.tx_dma_params;
1569
1570 if (channel == tx_params->dma_channel) {
1571 async_evt_tx_done(uart_dev);
1572 } else if (channel == rx_params->dma_channel) {
1573
1574 rx_params->counter = rx_params->buf_len;
1575
1576 async_evt_rx_rdy(uart_dev);
1577 async_evt_rx_buf_release(uart_dev);
1578
1579 rx_params->buf = data->async.next_rx_buffer;
1580 rx_params->buf_len = data->async.next_rx_buffer_len;
1581 data->async.next_rx_buffer = NULL;
1582 data->async.next_rx_buffer_len = 0U;
1583
1584 if (rx_params->buf != NULL &&
1585 rx_params->buf_len > 0) {
1586 dma_reload(dev, rx_params->dma_channel, data->phys_addr,
1587 (uintptr_t)rx_params->buf, rx_params->buf_len);
1588 dma_start(dev, rx_params->dma_channel);
1589 async_evt_rx_buf_request(uart_dev);
1590 } else {
1591 uart_ns16550_rx_disable(uart_dev);
1592 }
1593 }
1594 }
1595 #endif
1596
1597 static int uart_ns16550_callback_set(const struct device *dev, uart_callback_t callback,
1598 void *user_data)
1599 {
1600 struct uart_ns16550_dev_data *data = dev->data;
1601
1602 data->async.user_callback = callback;
1603 data->async.user_data = user_data;
1604
1605 return 0;
1606 }
1607
1608 static int uart_ns16550_tx(const struct device *dev, const uint8_t *buf, size_t len,
1609 int32_t timeout_us)
1610 {
1611 struct uart_ns16550_dev_data *data = dev->data;
1612 struct uart_ns16550_tx_dma_params *tx_params = &data->async.tx_dma_params;
1613 k_spinlock_key_t key = k_spin_lock(&data->lock);
1614 int ret = 0;
1615
1616 if (!device_is_ready(tx_params->dma_dev)) {
1617 ret = -ENODEV;
1618 goto out;
1619 }
1620
1621 tx_params->buf = buf;
1622 tx_params->buf_len = len;
1623 tx_params->active_dma_block.source_address = (uintptr_t)buf;
1624 tx_params->active_dma_block.dest_address = data->phys_addr;
1625 tx_params->active_dma_block.block_size = len;
1626 tx_params->active_dma_block.next_block = NULL;
1627
1628 ret = dma_config(tx_params->dma_dev,
1629 tx_params->dma_channel,
1630 (struct dma_config *)&tx_params->dma_cfg);
1631
1632 if (ret == 0) {
1633 ret = dma_start(tx_params->dma_dev,
1634 tx_params->dma_channel);
1635 if (ret) {
1636 ret = -EIO;
1637 goto out;
1638 }
1639 async_timer_start(&data->async.tx_dma_params.timeout_work, timeout_us);
1640 }
1641
1642 out:
1643 k_spin_unlock(&data->lock, key);
1644 return ret;
1645 }
1646
1647 static int uart_ns16550_tx_abort(const struct device *dev)
1648 {
1649 struct uart_ns16550_dev_data *data = dev->data;
1650 struct uart_ns16550_tx_dma_params *tx_params = &data->async.tx_dma_params;
1651 struct dma_status status;
1652 int ret = 0;
1653 size_t bytes_tx;
1654
1655 k_spinlock_key_t key = k_spin_lock(&data->lock);
1656
1657 if (!device_is_ready(tx_params->dma_dev)) {
1658 ret = -ENODEV;
1659 goto out;
1660 }
1661
1662 (void)k_work_cancel_delayable(&data->async.tx_dma_params.timeout_work);
1663
1664 ret = dma_stop(tx_params->dma_dev, tx_params->dma_channel);
1665 dma_get_status(tx_params->dma_dev,
1666 tx_params->dma_channel,
1667 &status);
1668 bytes_tx = tx_params->buf_len - status.pending_length;
1669
1670 if (ret == 0) {
1671 struct uart_event tx_aborted_event = {
1672 .type = UART_TX_ABORTED,
1673 .data.tx.buf = tx_params->buf,
1674 .data.tx.len = bytes_tx
1675 };
1676 async_user_callback(dev, &tx_aborted_event);
1677 }
1678 out:
1679 k_spin_unlock(&data->lock, key);
1680 return ret;
1681 }
1682
1683 static int uart_ns16550_rx_enable(const struct device *dev, uint8_t *buf, const size_t len,
1684 const int32_t timeout_us)
1685 {
1686 struct uart_ns16550_dev_data *data = dev->data;
1687 const struct uart_ns16550_dev_config *config = dev->config;
1688 struct uart_ns16550_rx_dma_params *rx_dma_params = &data->async.rx_dma_params;
1689 int ret = 0;
1690 k_spinlock_key_t key = k_spin_lock(&data->lock);
1691
1692 if (!device_is_ready(rx_dma_params->dma_dev)) {
1693 ret = -ENODEV;
1694 goto out;
1695 }
1696
1697 rx_dma_params->timeout_us = timeout_us;
1698 rx_dma_params->buf = buf;
1699 rx_dma_params->buf_len = len;
1700
1701 #if defined(CONFIG_UART_NS16550_INTEL_LPSS_DMA)
1702 ns16550_outword(config, MST(dev), UNMASK_LPSS_INT(rx_dma_params->dma_channel));
1703 #else
1704 ns16550_outbyte(config, IER(dev),
1705 (ns16550_inbyte(config, IER(dev)) | IER_RXRDY));
1706 ns16550_outbyte(config, FCR(dev), FCR_FIFO);
1707 #endif
1708 prepare_rx_dma_block_config(dev);
1709 dma_config(rx_dma_params->dma_dev,
1710 rx_dma_params->dma_channel,
1711 (struct dma_config *)&rx_dma_params->dma_cfg);
1712 dma_start(rx_dma_params->dma_dev, rx_dma_params->dma_channel);
1713 async_evt_rx_buf_request(dev);
1714 out:
1715 k_spin_unlock(&data->lock, key);
1716 return ret;
1717 }
1718
1719 static int uart_ns16550_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
1720 {
1721 struct uart_ns16550_dev_data *data = dev->data;
1722
1723 assert(data->async.next_rx_buffer == NULL);
1724 assert(data->async.next_rx_buffer_len == 0);
1725 data->async.next_rx_buffer = buf;
1726 data->async.next_rx_buffer_len = len;
1727
1728 return 0;
1729 }
1730
1731 static void uart_ns16550_async_rx_timeout(struct k_work *work)
1732 {
1733 struct k_work_delayable *work_delay = CONTAINER_OF(work, struct k_work_delayable, work);
1734 struct uart_ns16550_rx_dma_params *rx_params =
1735 CONTAINER_OF(work_delay, struct uart_ns16550_rx_dma_params,
1736 timeout_work);
1737 struct uart_ns16550_async_data *async_data =
1738 CONTAINER_OF(rx_params, struct uart_ns16550_async_data,
1739 rx_dma_params);
1740 const struct device *dev = async_data->uart_dev;
1741
1742 uart_ns16550_async_rx_flush(dev);
1743
1744 }
1745
1746 static void uart_ns16550_async_tx_timeout(struct k_work *work)
1747 {
1748 struct k_work_delayable *work_delay = CONTAINER_OF(work, struct k_work_delayable, work);
1749 struct uart_ns16550_tx_dma_params *tx_params =
1750 CONTAINER_OF(work_delay, struct uart_ns16550_tx_dma_params,
1751 timeout_work);
1752 struct uart_ns16550_async_data *async_data =
1753 CONTAINER_OF(tx_params, struct uart_ns16550_async_data,
1754 tx_dma_params);
1755 const struct device *dev = async_data->uart_dev;
1756
1757 (void)uart_ns16550_tx_abort(dev);
1758 }
1759
1760 #endif /* CONFIG_UART_ASYNC_API */
1761
1762 static DEVICE_API(uart, uart_ns16550_driver_api) = {
1763 .poll_in = uart_ns16550_poll_in,
1764 .poll_out = uart_ns16550_poll_out,
1765 .err_check = uart_ns16550_err_check,
1766 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
1767 .configure = uart_ns16550_configure,
1768 .config_get = uart_ns16550_config_get,
1769 #endif
1770 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1771
1772 .fifo_fill = uart_ns16550_fifo_fill,
1773 .fifo_read = uart_ns16550_fifo_read,
1774 .irq_tx_enable = uart_ns16550_irq_tx_enable,
1775 .irq_tx_disable = uart_ns16550_irq_tx_disable,
1776 .irq_tx_ready = uart_ns16550_irq_tx_ready,
1777 .irq_tx_complete = uart_ns16550_irq_tx_complete,
1778 .irq_rx_enable = uart_ns16550_irq_rx_enable,
1779 .irq_rx_disable = uart_ns16550_irq_rx_disable,
1780 .irq_rx_ready = uart_ns16550_irq_rx_ready,
1781 .irq_err_enable = uart_ns16550_irq_err_enable,
1782 .irq_err_disable = uart_ns16550_irq_err_disable,
1783 .irq_is_pending = uart_ns16550_irq_is_pending,
1784 .irq_update = uart_ns16550_irq_update,
1785 .irq_callback_set = uart_ns16550_irq_callback_set,
1786
1787 #endif
1788
1789 #ifdef CONFIG_UART_ASYNC_API
1790 .callback_set = uart_ns16550_callback_set,
1791 .tx = uart_ns16550_tx,
1792 .tx_abort = uart_ns16550_tx_abort,
1793 .rx_enable = uart_ns16550_rx_enable,
1794 .rx_disable = uart_ns16550_rx_disable,
1795 .rx_buf_rsp = uart_ns16550_rx_buf_rsp,
1796 #endif
1797
1798 #ifdef CONFIG_UART_NS16550_LINE_CTRL
1799 .line_ctrl_set = uart_ns16550_line_ctrl_set,
1800 #endif
1801
1802 #ifdef CONFIG_UART_NS16550_DRV_CMD
1803 .drv_cmd = uart_ns16550_drv_cmd,
1804 #endif
1805 };
1806
1807 #define UART_NS16550_IRQ_FLAGS(n) \
1808 COND_CODE_1(DT_INST_IRQ_HAS_CELL(n, sense), \
1809 (DT_INST_IRQ(n, sense)), \
1810 (0))
1811
1812 /* IO-port or MMIO based UART */
1813 #define UART_NS16550_IRQ_CONFIG(n) \
1814 static void uart_ns16550_irq_config_func##n(const struct device *dev) \
1815 { \
1816 ARG_UNUSED(dev); \
1817 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
1818 uart_ns16550_isr, DEVICE_DT_INST_GET(n), \
1819 UART_NS16550_IRQ_FLAGS(n)); \
1820 irq_enable(DT_INST_IRQN(n)); \
1821 }
1822
1823 /* PCI(e) with auto IRQ detection */
1824 #define UART_NS16550_IRQ_CONFIG_PCIE(n) \
1825 static void uart_ns16550_irq_config_func##n(const struct device *dev) \
1826 { \
1827 BUILD_ASSERT(DT_INST_IRQN(n) == PCIE_IRQ_DETECT, \
1828 "Only runtime IRQ configuration is supported"); \
1829 BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS), \
1830 "NS16550 PCIe requires dynamic interrupts"); \
1831 const struct uart_ns16550_dev_config *dev_cfg = dev->config; \
1832 unsigned int irq = pcie_alloc_irq(dev_cfg->pcie->bdf); \
1833 if (irq == PCIE_CONF_INTR_IRQ_NONE) { \
1834 return; \
1835 } \
1836 pcie_connect_dynamic_irq(dev_cfg->pcie->bdf, irq, \
1837 DT_INST_IRQ(n, priority), \
1838 (void (*)(const void *))uart_ns16550_isr, \
1839 DEVICE_DT_INST_GET(n), \
1840 UART_NS16550_IRQ_FLAGS(n)); \
1841 pcie_irq_enable(dev_cfg->pcie->bdf, irq); \
1842 }
1843
1844 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1845 #define DEV_CONFIG_IRQ_FUNC_INIT(n) \
1846 .irq_config_func = uart_ns16550_irq_config_func##n,
1847 #define UART_NS16550_IRQ_FUNC_DECLARE(n) \
1848 static void uart_ns16550_irq_config_func##n(const struct device *dev);
1849 #define UART_NS16550_IRQ_FUNC_DEFINE(n) \
1850 UART_NS16550_IRQ_CONFIG(n)
1851
1852 #define DEV_CONFIG_PCIE_IRQ_FUNC_INIT(n) \
1853 .irq_config_func = uart_ns16550_irq_config_func##n,
1854 #define UART_NS16550_PCIE_IRQ_FUNC_DECLARE(n) \
1855 static void uart_ns16550_irq_config_func##n(const struct device *dev);
1856 #define UART_NS16550_PCIE_IRQ_FUNC_DEFINE(n) \
1857 UART_NS16550_IRQ_CONFIG_PCIE(n)
1858 #else
1859 /* !CONFIG_UART_INTERRUPT_DRIVEN */
1860 #define DEV_CONFIG_IRQ_FUNC_INIT(n)
1861 #define UART_NS16550_IRQ_FUNC_DECLARE(n)
1862 #define UART_NS16550_IRQ_FUNC_DEFINE(n)
1863
1864 #define DEV_CONFIG_PCIE_IRQ_FUNC_INIT(n)
1865 #define UART_NS16550_PCIE_IRQ_FUNC_DECLARE(n)
1866 #define UART_NS16550_PCIE_IRQ_FUNC_DEFINE(n)
1867 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1868
1869 #ifdef CONFIG_UART_ASYNC_API
1870 #define DMA_PARAMS(n) \
1871 .async.tx_dma_params = { \
1872 .dma_dev = \
1873 DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, tx)), \
1874 .dma_channel = \
1875 DT_INST_DMAS_CELL_BY_NAME(n, tx, channel), \
1876 .dma_cfg = { \
1877 .source_burst_length = 1, \
1878 .dest_burst_length = 1, \
1879 .source_data_size = 1, \
1880 .dest_data_size = 1, \
1881 .complete_callback_en = 0, \
1882 .error_callback_dis = 1, \
1883 .block_count = 1, \
1884 .channel_direction = MEMORY_TO_PERIPHERAL, \
1885 .dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, tx, channel), \
1886 .dma_callback = dma_callback, \
1887 .user_data = (void *)DEVICE_DT_INST_GET(n) \
1888 }, \
1889 }, \
1890 .async.rx_dma_params = { \
1891 .dma_dev = \
1892 DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, rx)), \
1893 .dma_channel = \
1894 DT_INST_DMAS_CELL_BY_NAME(n, rx, channel), \
1895 .dma_cfg = { \
1896 .source_burst_length = 1, \
1897 .dest_burst_length = 1, \
1898 .source_data_size = 1, \
1899 .dest_data_size = 1, \
1900 .complete_callback_en = 0, \
1901 .error_callback_dis = 1, \
1902 .block_count = 1, \
1903 .channel_direction = PERIPHERAL_TO_MEMORY, \
1904 .dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, rx, channel), \
1905 .dma_callback = dma_callback, \
1906 .user_data = (void *)DEVICE_DT_INST_GET(n) \
1907 }, \
1908 }, \
1909 COND_CODE_0(DT_INST_ON_BUS(n, pcie), \
1910 (.phys_addr = DT_INST_REG_ADDR(n),), ())
1911
1912 #define DMA_PARAMS_NULL(n) \
1913 .async.tx_dma_params = { \
1914 .dma_dev = NULL \
1915 }, \
1916 .async.rx_dma_params = { \
1917 .dma_dev = NULL \
1918 }, \
1919
1920 #define DEV_DATA_ASYNC(n) \
1921 COND_CODE_0(DT_INST_PROP(n, io_mapped), \
1922 (COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
1923 (DMA_PARAMS(n)), (DMA_PARAMS_NULL(n)))), \
1924 (DMA_PARAMS_NULL(n)))
1925 #else
1926 #define DEV_DATA_ASYNC(n)
1927 #endif /* CONFIG_UART_ASYNC_API */
1928
1929
1930 #define UART_NS16550_COMMON_DEV_CFG_INITIALIZER(n) \
1931 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, clock_frequency), ( \
1932 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
1933 .clock_dev = NULL, \
1934 .clock_subsys = NULL, \
1935 ), ( \
1936 .sys_clk_freq = 0, \
1937 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
1938 .clock_subsys = (clock_control_subsys_t) DT_INST_PHA(\
1939 0, clocks, clkid), \
1940 ) \
1941 ) \
1942 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pcp), \
1943 (.pcp = DT_INST_PROP_OR(n, pcp, 0),)) \
1944 .reg_interval = (1 << DT_INST_PROP(n, reg_shift)), \
1945 IF_ENABLED(CONFIG_PINCTRL, \
1946 (.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),)) \
1947 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, resets), \
1948 (.reset_spec = RESET_DT_SPEC_INST_GET(n),))
1949
1950 #define UART_NS16550_COMMON_DEV_DATA_INITIALIZER(n) \
1951 .uart_config.baudrate = DT_INST_PROP_OR(n, current_speed, 0), \
1952 .uart_config.parity = UART_CFG_PARITY_NONE, \
1953 .uart_config.stop_bits = UART_CFG_STOP_BITS_1, \
1954 .uart_config.data_bits = UART_CFG_DATA_BITS_8, \
1955 .uart_config.flow_ctrl = \
1956 COND_CODE_1(DT_INST_PROP_OR(n, hw_flow_control, 0), \
1957 (UART_CFG_FLOW_CTRL_RTS_CTS), \
1958 (UART_CFG_FLOW_CTRL_NONE)), \
1959 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, dlf), \
1960 (.dlf = DT_INST_PROP_OR(n, dlf, 0),)) \
1961 DEV_DATA_ASYNC(n) \
1962
1963 #define UART_NS16550_DEVICE_IO_MMIO_INIT(n) \
1964 UART_NS16550_IRQ_FUNC_DECLARE(n); \
1965 IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_INST_DEFINE(n))); \
1966 static const struct uart_ns16550_dev_config uart_ns16550_dev_cfg_##n = { \
1967 COND_CODE_1(DT_INST_PROP_OR(n, io_mapped, 0), \
1968 (.port = DT_INST_REG_ADDR(n),), \
1969 (DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),)) \
1970 IF_ENABLED(DT_INST_PROP_OR(n, io_mapped, 0), \
1971 (.io_map = true,)) \
1972 UART_NS16550_COMMON_DEV_CFG_INITIALIZER(n) \
1973 DEV_CONFIG_IRQ_FUNC_INIT(n) \
1974 }; \
1975 static struct uart_ns16550_dev_data uart_ns16550_dev_data_##n = { \
1976 UART_NS16550_COMMON_DEV_DATA_INITIALIZER(n) \
1977 }; \
1978 DEVICE_DT_INST_DEFINE(n, uart_ns16550_init, NULL, \
1979 &uart_ns16550_dev_data_##n, &uart_ns16550_dev_cfg_##n, \
1980 PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
1981 &uart_ns16550_driver_api); \
1982 UART_NS16550_IRQ_FUNC_DEFINE(n)
1983
1984 #define UART_NS16550_DEVICE_PCIE_INIT(n) \
1985 UART_NS16550_PCIE_IRQ_FUNC_DECLARE(n); \
1986 DEVICE_PCIE_INST_DECLARE(n); \
1987 IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_INST_DEFINE(n))); \
1988 static const struct uart_ns16550_dev_config uart_ns16550_dev_cfg_##n = { \
1989 UART_NS16550_COMMON_DEV_CFG_INITIALIZER(n) \
1990 DEV_CONFIG_PCIE_IRQ_FUNC_INIT(n) \
1991 DEVICE_PCIE_INST_INIT(n, pcie) \
1992 }; \
1993 static struct uart_ns16550_dev_data uart_ns16550_dev_data_##n = { \
1994 UART_NS16550_COMMON_DEV_DATA_INITIALIZER(n) \
1995 }; \
1996 DEVICE_DT_INST_DEFINE(n, uart_ns16550_init, NULL, \
1997 &uart_ns16550_dev_data_##n, &uart_ns16550_dev_cfg_##n, \
1998 PRE_KERNEL_1, \
1999 CONFIG_SERIAL_INIT_PRIORITY, \
2000 &uart_ns16550_driver_api); \
2001 UART_NS16550_PCIE_IRQ_FUNC_DEFINE(n)
2002
2003 #define UART_NS16550_DEVICE_INIT(n) \
2004 COND_CODE_1(DT_INST_ON_BUS(n, pcie), \
2005 (UART_NS16550_DEVICE_PCIE_INIT(n)), \
2006 (UART_NS16550_DEVICE_IO_MMIO_INIT(n)))
2007
2008 DT_INST_FOREACH_STATUS_OKAY(UART_NS16550_DEVICE_INIT)
2009
