__INSTANCE__ (reference) in projects: hal_stm32-3.5.0

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Searched refs:__INSTANCE__ (Results 1 – 25 of 553) sorted by relevance

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/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/include/
D	stm32f4xx_ll_fmc.h	95 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) argument 96 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) argument 126 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) argument 130 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE) argument 168 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) argument 982 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 991 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 1013 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN) argument 1015 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)… argument 1016 … ((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN)) [all …]
D	stm32f4xx_ll_fsmc.h	95 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) argument 96 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVI… argument 122 #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) argument 126 #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) argument 769 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 778 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 798 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE_… argument 799 … ((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN)) 807 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__… argument 808 … CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN)) [all …]
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/include/
D	stm32h5xx_hal_lptim.h	`1118 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ argument 1119 ((((__INSTANCE__) == LPTIM1) && \ 1124 (((__INSTANCE__) == LPTIM2) && \ 1129 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ argument 1130 ((((__INSTANCE__) == LPTIM1) \|\| \ 1131 ((__INSTANCE__) == LPTIM2) \|\| \ 1132 ((__INSTANCE__) == LPTIM3) \|\| \ 1133 ((__INSTANCE__) == LPTIM4) \|\| \ 1134 ((__INSTANCE__) == LPTIM5) \|\| \ 1135 ((__INSTANCE__) == LPTIM6)) && \ [all …]`
D	stm32h5xx_ll_fmc.h	94 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) argument 95 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) argument 119 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) argument 154 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) argument 920 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 929 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 946 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN) argument 954 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) argument 975 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__)) argument 987 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) argument [all …]
D	stm32h5xx_ll_sdmmc.h	767 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__)) argument 799 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) argument 837 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) argument 867 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) argument 899 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__… argument 927 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) argument 934 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART) argument 941 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTAR… argument 948 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP) argument 955 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) argument [all …]
/hal_stm32-3.5.0/stm32cube/stm32f2xx/drivers/include/
D	stm32f2xx_ll_fsmc.h	85 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) argument 86 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVI… argument 109 #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) argument 111 #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) argument 588 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 597 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 615 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE_… argument 616 … ((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN)) 624 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__… argument 625 … CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN)) [all …]
/hal_stm32-3.5.0/stm32cube/stm32f3xx/drivers/include/
D	stm32f3xx_ll_fmc.h	86 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) argument 87 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) argument 112 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) argument 116 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE) argument 629 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 638 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 658 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)… argument 659 … ((__INSTANCE__)->PCR3 \|= FMC_PCRx_PBKEN)) 667 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__IN… argument 668 … CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN)) [all …]
/hal_stm32-3.5.0/stm32cube/stm32f1xx/drivers/include/
D	stm32f1xx_ll_fsmc.h	92 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) argument 93 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVI… argument 118 #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) argument 122 #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) argument 646 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 655 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 675 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE_… argument 676 … ((__INSTANCE__)->PCR3 \|= FSMC_PCRx_PBKEN)) 684 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__… argument 685 … CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) [all …]
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/include/
D	stm32wbaxx_hal_lptim.h	1110 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ argument 1111 ((((__INSTANCE__) == LPTIM1) \|\| \ 1112 ((__INSTANCE__) == LPTIM2)) && \ 1116 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ argument 1117 ((((__INSTANCE__) == LPTIM1) \|\| \ 1118 ((__INSTANCE__) == LPTIM2)) && \ 1123 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ argument 1124 (((__INSTANCE__) == LPTIM1) && \ 1128 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ argument 1129 (((__INSTANCE__) == LPTIM1) && \ [all …]
/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/include/
D	stm32l4xx_ll_sdmmc.h	841 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR \|= SDMMC_CLKCR_CLKEN) argument 848 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) argument 855 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_DMAEN) argument 862 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) argument 902 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__)) argument 941 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) argument 984 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) argument 1014 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) argument 1053 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__… argument 1081 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) argument [all …]
/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/include/
D	stm32f7xx_ll_sdmmc.h	671 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR \|= SDMMC_CLKCR_CLKEN) argument 678 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) argument 685 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_DMAEN) argument 692 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) argument 723 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__)) argument 754 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) argument 785 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) argument 806 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) argument 837 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (… 856 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) argument [all …]
D	stm32f7xx_ll_fmc.h	90 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) argument 91 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) argument 114 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) argument 150 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) argument 877 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 886 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 903 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN) argument 911 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) argument 932 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__)) argument 944 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) argument [all …]
/hal_stm32-3.5.0/stm32cube/stm32l0xx/drivers/include/
D	stm32l0xx_hal_tim_ex.h	153 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ argument 154 ((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP \| TIM2_OR_ETR_RMP))) \|\| \ 155 (((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP \| TIM22_OR_ETR_RMP))) \|\| \ 156 …(((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP \| TIM21_OR_TI1_RMP \| TIM21_… 157 …(((__INSTANCE__) == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP \| TIM3_OR_TI1_RMP \| TIM3_O… 159 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ argument 160 ((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \ 164 (((__INSTANCE__) == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \ 168 (((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \ 170 (((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \ [all …]
/hal_stm32-3.5.0/stm32cube/stm32mp1xx/drivers/include/
D	stm32mp1xx_ll_sdmmc.h	707 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__)) argument 739 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) argument 777 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) argument 807 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) argument 845 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (… 874 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) argument 881 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART) argument 888 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTAR… argument 895 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP) argument 902 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) argument [all …]
/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/include/
D	stm32h7xx_ll_fmc.h	90 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) argument 91 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) argument 114 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) argument 150 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) argument 888 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 897 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ argument 914 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN) argument 922 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) argument 943 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__)) argument 955 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) argument [all …]
D	stm32h7xx_ll_sdmmc.h	740 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__)) argument 772 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) argument 810 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) argument 840 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) argument 872 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__… argument 900 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) argument 907 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART) argument 914 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTAR… argument 921 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP) argument 928 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) argument [all …]
/hal_stm32-3.5.0/stm32cube/stm32l5xx/drivers/include/
D	stm32l5xx_ll_sdmmc.h	736 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__)) argument 768 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) argument 806 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) argument 836 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) argument 868 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__… argument 896 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) argument 903 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART) argument 910 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTAR… argument 917 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP) argument 924 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) argument [all …]
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/include/
D	stm32u5xx_hal_lptim.h	`1104 #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ argument 1105 ((((__INSTANCE__) == LPTIM1) \|\| \ 1106 ((__INSTANCE__) == LPTIM2) \|\| \ 1107 ((__INSTANCE__) == LPTIM3) \|\| \ 1108 ((__INSTANCE__) == LPTIM4)) && \ 1112 #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ argument 1113 ((((__INSTANCE__) == LPTIM1) \|\| \ 1114 ((__INSTANCE__) == LPTIM2)) && \ 1118 #define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ argument 1119 ((((__INSTANCE__) == LPTIM1) \|\| \ [all …]`
D	stm32u5xx_ll_sdmmc.h	769 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__)) argument 801 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) argument 839 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) argument 869 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) argument 901 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__… argument 929 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) argument 936 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART) argument 943 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTAR… argument 950 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP) argument 957 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) argument [all …]
/hal_stm32-3.5.0/stm32cube/stm32f7xx/soc/
D	stm32f723xx.h	15000 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) \|\| \ argument 15001 ((__INSTANCE__) == ADC2) \|\| \ 15002 ((__INSTANCE__) == ADC3)) 15008 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CAN1) argument 15010 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC) argument 15013 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1) argument 15019 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) \|\| \ argument 15020 ((__INSTANCE__) == DMA1_Stream1) \|\| \ 15021 ((__INSTANCE__) == DMA1_Stream2) \|\| \ 15022 ((__INSTANCE__) == DMA1_Stream3) \|\| \ [all …]
D	stm32f722xx.h	14906 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) \|\| \ argument 14907 ((__INSTANCE__) == ADC2) \|\| \ 14908 ((__INSTANCE__) == ADC3)) 14914 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CAN1) argument 14916 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC) argument 14919 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1) argument 14925 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) \|\| \ argument 14926 ((__INSTANCE__) == DMA1_Stream1) \|\| \ 14927 ((__INSTANCE__) == DMA1_Stream2) \|\| \ 14928 ((__INSTANCE__) == DMA1_Stream3) \|\| \ [all …]
D	stm32f730xx.h	15223 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) \|\| \ argument 15224 ((__INSTANCE__) == ADC2) \|\| \ 15225 ((__INSTANCE__) == ADC3)) 15231 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CAN1) argument 15233 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC) argument 15236 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1) argument 15242 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) \|\| \ argument 15243 ((__INSTANCE__) == DMA1_Stream1) \|\| \ 15244 ((__INSTANCE__) == DMA1_Stream2) \|\| \ 15245 ((__INSTANCE__) == DMA1_Stream3) \|\| \ [all …]
D	stm32f732xx.h	15129 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) \|\| \ argument 15130 ((__INSTANCE__) == ADC2) \|\| \ 15131 ((__INSTANCE__) == ADC3)) 15137 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CAN1) argument 15139 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC) argument 15142 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1) argument 15148 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) \|\| \ argument 15149 ((__INSTANCE__) == DMA1_Stream1) \|\| \ 15150 ((__INSTANCE__) == DMA1_Stream2) \|\| \ 15151 ((__INSTANCE__) == DMA1_Stream3) \|\| \ [all …]
D	stm32f733xx.h	15223 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) \|\| \ argument 15224 ((__INSTANCE__) == ADC2) \|\| \ 15225 ((__INSTANCE__) == ADC3)) 15231 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CAN1) argument 15233 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC) argument 15236 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1) argument 15242 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) \|\| \ argument 15243 ((__INSTANCE__) == DMA1_Stream1) \|\| \ 15244 ((__INSTANCE__) == DMA1_Stream2) \|\| \ 15245 ((__INSTANCE__) == DMA1_Stream3) \|\| \ [all …]
D	stm32f765xx.h	17680 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) \|\| \ argument 17681 ((__INSTANCE__) == ADC2) \|\| \ 17682 ((__INSTANCE__) == ADC3)) 17688 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) \|\| \ argument 17689 ((__INSTANCE__) == CAN2) \|\| \ 17690 ((__INSTANCE__) == CAN3)) 17692 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC) argument 17695 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1) argument 17698 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) argument 17716 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) argument [all …]

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TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
babblesim_base-3.7.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
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edtt-3.7.0
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hal_renesas-3.4.0
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