1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F7xx_LL_SDMMC_H 21 #define STM32F7xx_LL_SDMMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(SDMMC1) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32f7xx_hal_def.h" 31 32 /** @addtogroup STM32F7xx_Driver 33 * @{ 34 */ 35 36 /** @addtogroup SDMMC_LL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief SDMMC Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 51 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 52 53 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is 54 enabled or disabled. 55 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ 56 57 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 58 disabled when the bus is idle. 59 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 60 61 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 62 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 63 64 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 65 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 66 67 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 68 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 69 70 }SDMMC_InitTypeDef; 71 72 73 /** 74 * @brief SDMMC Command Control structure 75 */ 76 typedef struct 77 { 78 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 79 to a card as part of a command message. If a command 80 contains an argument, it must be loaded into this register 81 before writing the command to the command register. */ 82 83 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 84 Max_Data = 64 */ 85 86 uint32_t Response; /*!< Specifies the SDMMC response type. 87 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 88 89 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 90 enabled or disabled. 91 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 92 93 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 94 is enabled or disabled. 95 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 96 }SDMMC_CmdInitTypeDef; 97 98 99 /** 100 * @brief SDMMC Data Control structure 101 */ 102 typedef struct 103 { 104 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 105 106 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 107 108 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 109 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 110 111 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 112 is a read or write. 113 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 114 115 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 116 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 117 118 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 119 is enabled or disabled. 120 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 121 }SDMMC_DataInitTypeDef; 122 123 /** 124 * @} 125 */ 126 127 /* Exported constants --------------------------------------------------------*/ 128 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 129 * @{ 130 */ 131 #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ 132 #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ 133 #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ 134 #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ 135 #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ 136 #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ 137 #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ 138 #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ 139 #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the 140 number of transferred bytes does not match the block length */ 141 #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ 142 #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ 143 #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ 144 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock 145 command or if there was an attempt to access a locked card */ 146 #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ 147 #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ 148 #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ 149 #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ 150 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ 151 #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ 152 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ 153 #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ 154 #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ 155 #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ 156 #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out 157 of erase sequence command was received */ 158 #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ 159 #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ 160 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ 161 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ 162 #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ 163 #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ 164 #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ 165 #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ 166 #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ 167 168 /** 169 * @brief SDMMC Commands Index 170 */ 171 #define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ 172 #define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ 173 #define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 174 #define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ 175 #define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ 176 #define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 177 operating condition register (OCR) content in the response on the CMD line. */ 178 #define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 179 #define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ 180 #define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 181 and asks the card whether card supports voltage. */ 182 #define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 183 #define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ 184 #define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ 185 #define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ 186 #define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ 187 #define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ 188 #define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ 189 #define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands 190 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 191 for SDHS and SDXC. */ 192 #define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 193 fixed 512 bytes in case of SDHC and SDXC. */ 194 #define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by 195 STOP_TRANSMISSION command. */ 196 #define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 197 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ 198 #define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ 199 #define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 200 fixed 512 bytes in case of SDHC and SDXC. */ 201 #define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 202 #define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ 203 #define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ 204 #define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ 205 #define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ 206 #define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ 207 #define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ 208 #define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ 209 #define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command 210 system set by switch function command (CMD6). */ 211 #define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. 212 Reserved for each command system set by switch function command (CMD6). */ 213 #define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ 214 #define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ 215 #define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ 216 #define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 217 the SET_BLOCK_LEN command. */ 218 #define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather 219 than a standard command. */ 220 #define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card 221 for general purpose/application specific commands. */ 222 #define SDMMC_CMD_NO_CMD 64U /*!< No command */ 223 224 /** 225 * @brief Following commands are SD Card Specific commands. 226 * SDMMC_APP_CMD should be sent before sending these commands. 227 */ 228 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 229 widths are given in SCR register. */ 230 #define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ 231 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 232 32bit+CRC data block. */ 233 #define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 234 send its operating condition register (OCR) content in the response on the CMD line. */ 235 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 236 #define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ 237 #define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ 238 #define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ 239 240 /** 241 * @brief Following commands are SD Card Specific security commands. 242 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 243 */ 244 #define SDMMC_CMD_SD_APP_GET_MKB 43U 245 #define SDMMC_CMD_SD_APP_GET_MID 44U 246 #define SDMMC_CMD_SD_APP_SET_CER_RN1 45U 247 #define SDMMC_CMD_SD_APP_GET_CER_RN2 46U 248 #define SDMMC_CMD_SD_APP_SET_CER_RES2 47U 249 #define SDMMC_CMD_SD_APP_GET_CER_RES1 48U 250 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U 251 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U 252 #define SDMMC_CMD_SD_APP_SECURE_ERASE 38U 253 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U 254 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U 255 256 /** 257 * @brief Masks for errors Card Status R1 (OCR Register) 258 */ 259 #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U 260 #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U 261 #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U 262 #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U 263 #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U 264 #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U 265 #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U 266 #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U 267 #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U 268 #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U 269 #define SDMMC_OCR_CC_ERROR 0x00100000U 270 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U 271 #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U 272 #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U 273 #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U 274 #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U 275 #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U 276 #define SDMMC_OCR_ERASE_RESET 0x00002000U 277 #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U 278 #define SDMMC_OCR_ERRORBITS 0xFDFFE008U 279 280 /** 281 * @brief Masks for R6 Response 282 */ 283 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U 284 #define SDMMC_R6_ILLEGAL_CMD 0x00004000U 285 #define SDMMC_R6_COM_CRC_FAILED 0x00008000U 286 287 #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U 288 #define SDMMC_HIGH_CAPACITY 0x40000000U 289 #define SDMMC_STD_CAPACITY 0x00000000U 290 #define SDMMC_CHECK_PATTERN 0x000001AAU 291 #define SD_SWITCH_1_8V_CAPACITY 0x01000000U 292 293 #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU 294 295 #define SDMMC_MAX_TRIAL 0x0000FFFFU 296 297 #define SDMMC_ALLZERO 0x00000000U 298 299 #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U 300 #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U 301 #define SDMMC_CARD_LOCKED 0x02000000U 302 303 #ifndef SDMMC_DATATIMEOUT 304 #define SDMMC_DATATIMEOUT 0xFFFFFFFFU 305 #endif /* SDMMC_DATATIMEOUT */ 306 307 #define SDMMC_0TO7BITS 0x000000FFU 308 #define SDMMC_8TO15BITS 0x0000FF00U 309 #define SDMMC_16TO23BITS 0x00FF0000U 310 #define SDMMC_24TO31BITS 0xFF000000U 311 #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU 312 313 #define SDMMC_HALFFIFO 0x00000008U 314 #define SDMMC_HALFFIFOBYTES 0x00000020U 315 316 /** 317 * @brief Command Class supported 318 */ 319 #define SDMMC_CCCC_ERASE 0x00000020U 320 321 #define SDMMC_CMDTIMEOUT 5000U /* Command send and response timeout */ 322 #define SDMMC_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ 323 #define SDMMC_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */ 324 325 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 326 * @{ 327 */ 328 #define SDMMC_CLOCK_EDGE_RISING 0x00000000U 329 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 330 331 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 332 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 333 /** 334 * @} 335 */ 336 337 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass 338 * @{ 339 */ 340 #define SDMMC_CLOCK_BYPASS_DISABLE 0x00000000U 341 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS 342 343 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ 344 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) 345 /** 346 * @} 347 */ 348 349 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 350 * @{ 351 */ 352 #define SDMMC_CLOCK_POWER_SAVE_DISABLE 0x00000000U 353 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 354 355 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 356 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 357 /** 358 * @} 359 */ 360 361 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 362 * @{ 363 */ 364 #define SDMMC_BUS_WIDE_1B 0x00000000U 365 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 366 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 367 368 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 369 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 370 ((WIDE) == SDMMC_BUS_WIDE_8B)) 371 /** 372 * @} 373 */ 374 375 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 376 * @{ 377 */ 378 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U 379 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 380 381 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 382 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 383 /** 384 * @} 385 */ 386 387 /** @defgroup SDMMC_LL_Clock_Division Clock Division 388 * @{ 389 */ 390 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) 391 /** 392 * @} 393 */ 394 395 /** @defgroup SDMMC_LL_Command_Index Command Index 396 * @{ 397 */ 398 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 399 /** 400 * @} 401 */ 402 403 /** @defgroup SDMMC_LL_Response_Type Response Type 404 * @{ 405 */ 406 #define SDMMC_RESPONSE_NO 0x00000000U 407 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 408 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 409 410 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 411 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 412 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 413 /** 414 * @} 415 */ 416 417 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 418 * @{ 419 */ 420 #define SDMMC_WAIT_NO 0x00000000U 421 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 422 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 423 424 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 425 ((WAIT) == SDMMC_WAIT_IT) || \ 426 ((WAIT) == SDMMC_WAIT_PEND)) 427 /** 428 * @} 429 */ 430 431 /** @defgroup SDMMC_LL_CPSM_State CPSM State 432 * @{ 433 */ 434 #define SDMMC_CPSM_DISABLE 0x00000000U 435 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 436 437 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 438 ((CPSM) == SDMMC_CPSM_ENABLE)) 439 /** 440 * @} 441 */ 442 443 /** @defgroup SDMMC_LL_Response_Registers Response Register 444 * @{ 445 */ 446 #define SDMMC_RESP1 0x00000000U 447 #define SDMMC_RESP2 0x00000004U 448 #define SDMMC_RESP3 0x00000008U 449 #define SDMMC_RESP4 0x0000000CU 450 451 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 452 ((RESP) == SDMMC_RESP2) || \ 453 ((RESP) == SDMMC_RESP3) || \ 454 ((RESP) == SDMMC_RESP4)) 455 /** 456 * @} 457 */ 458 459 /** @defgroup SDMMC_LL_Data_Length Data Length 460 * @{ 461 */ 462 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 463 /** 464 * @} 465 */ 466 467 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 468 * @{ 469 */ 470 #define SDMMC_DATABLOCK_SIZE_1B 0x00000000U 471 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 472 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 473 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 474 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 475 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 476 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 477 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 478 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 479 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 480 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 481 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 482 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 483 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 484 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 485 486 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 487 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 488 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 489 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 490 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 491 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 492 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 493 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 494 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 495 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 496 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 497 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 498 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 499 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 500 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 501 /** 502 * @} 503 */ 504 505 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 506 * @{ 507 */ 508 #define SDMMC_TRANSFER_DIR_TO_CARD 0x00000000U 509 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 510 511 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 512 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 513 /** 514 * @} 515 */ 516 517 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 518 * @{ 519 */ 520 #define SDMMC_TRANSFER_MODE_BLOCK 0x00000000U 521 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE 522 523 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 524 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 525 /** 526 * @} 527 */ 528 529 /** @defgroup SDMMC_LL_DPSM_State DPSM State 530 * @{ 531 */ 532 #define SDMMC_DPSM_DISABLE 0x00000000U 533 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 534 535 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 536 ((DPSM) == SDMMC_DPSM_ENABLE)) 537 /** 538 * @} 539 */ 540 541 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 542 * @{ 543 */ 544 #define SDMMC_READ_WAIT_MODE_DATA2 0x00000000U 545 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 546 547 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 548 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 549 /** 550 * @} 551 */ 552 553 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 554 * @{ 555 */ 556 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 557 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 558 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 559 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 560 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 561 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 562 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 563 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 564 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 565 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 566 #define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE 567 #define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE 568 #define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE 569 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 570 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 571 #define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE 572 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 573 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 574 #define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE 575 #define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE 576 #define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE 577 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 578 /** 579 * @} 580 */ 581 582 /** @defgroup SDMMC_LL_Flags Flags 583 * @{ 584 */ 585 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 586 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 587 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 588 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 589 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 590 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 591 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 592 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 593 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 594 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 595 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT 596 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT 597 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT 598 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 599 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 600 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 601 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 602 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 603 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 604 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL 605 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL 606 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 607 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 608 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 609 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 610 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) 611 612 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 613 SDMMC_FLAG_CMDSENT)) 614 615 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 616 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) 617 /** 618 * @} 619 */ 620 621 /** 622 * @} 623 */ 624 625 /* Exported macro ------------------------------------------------------------*/ 626 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 627 * @{ 628 */ 629 630 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 631 * @brief SDMMC_LL registers bit address in the alias region 632 * @{ 633 */ 634 /* ---------------------- SDMMC registers bit mask --------------------------- */ 635 /* --- CLKCR Register ---*/ 636 /* CLKCR register clear mask */ 637 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 638 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ 639 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 640 641 /* --- DCTRL Register ---*/ 642 /* SDMMC DCTRL Clear Mask */ 643 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 644 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 645 646 /* --- CMD Register ---*/ 647 /* CMD Register clear mask */ 648 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 649 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 650 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) 651 652 /* SDMMC Initialization Frequency (400KHz max) */ 653 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ 654 655 /* SDMMC Data Transfer Frequency (25MHz max) */ 656 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ 657 /** 658 * @} 659 */ 660 661 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 662 * @brief macros to handle interrupts and specific clock configurations 663 * @{ 664 */ 665 666 /** 667 * @brief Enable the SDMMC device. 668 * @param __INSTANCE__: SDMMC Instance 669 * @retval None 670 */ 671 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) 672 673 /** 674 * @brief Disable the SDMMC device. 675 * @param __INSTANCE__: SDMMC Instance 676 * @retval None 677 */ 678 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) 679 680 /** 681 * @brief Enable the SDMMC DMA transfer. 682 * @param __INSTANCE__: SDMMC Instance 683 * @retval None 684 */ 685 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) 686 687 /** 688 * @brief Disable the SDMMC DMA transfer. 689 * @param __INSTANCE__: SDMMC Instance 690 * @retval None 691 */ 692 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) 693 694 /** 695 * @brief Enable the SDMMC device interrupt. 696 * @param __INSTANCE__ : Pointer to SDMMC register base 697 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. 698 * This parameter can be one or a combination of the following values: 699 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 700 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 701 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 702 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 703 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 704 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 705 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 706 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 707 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 708 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 709 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 710 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 711 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 712 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 713 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 714 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 715 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 716 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 717 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 718 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 719 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 720 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 721 * @retval None 722 */ 723 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 724 725 /** 726 * @brief Disable the SDMMC device interrupt. 727 * @param __INSTANCE__ : Pointer to SDMMC register base 728 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. 729 * This parameter can be one or a combination of the following values: 730 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 731 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 732 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 733 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 734 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 735 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 736 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 737 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 738 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 739 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 740 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 741 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 742 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 743 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 744 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 745 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 746 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 747 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 748 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 749 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 750 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 751 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 752 * @retval None 753 */ 754 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 755 756 /** 757 * @brief Checks whether the specified SDMMC flag is set or not. 758 * @param __INSTANCE__ : Pointer to SDMMC register base 759 * @param __FLAG__: specifies the flag to check. 760 * This parameter can be one of the following values: 761 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 762 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 763 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 764 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 765 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 766 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 767 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 768 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 769 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 770 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 771 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress 772 * @arg SDMMC_FLAG_TXACT: Data transmit in progress 773 * @arg SDMMC_FLAG_RXACT: Data receive in progress 774 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 775 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 776 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 777 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 778 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 779 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 780 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO 781 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO 782 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 783 * @retval The new state of SDMMC_FLAG (SET or RESET). 784 */ 785 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 786 787 788 /** 789 * @brief Clears the SDMMC pending flags. 790 * @param __INSTANCE__ : Pointer to SDMMC register base 791 * @param __FLAG__: specifies the flag to clear. 792 * This parameter can be one or a combination of the following values: 793 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 794 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 795 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 796 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 797 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 798 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 799 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 800 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 801 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 802 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 803 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 804 * @retval None 805 */ 806 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 807 808 /** 809 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 810 * @param __INSTANCE__ : Pointer to SDMMC register base 811 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. 812 * This parameter can be one of the following values: 813 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 814 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 815 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 816 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 817 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 818 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 819 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 820 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 821 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 822 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 823 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 824 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 825 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 826 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 827 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 828 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 829 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 830 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 831 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 832 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 833 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 834 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 835 * @retval The new state of SDMMC_IT (SET or RESET). 836 */ 837 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 838 839 /** 840 * @brief Clears the SDMMC's interrupt pending bits. 841 * @param __INSTANCE__ : Pointer to SDMMC register base 842 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 843 * This parameter can be one or a combination of the following values: 844 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 845 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 846 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 847 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 848 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 849 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 850 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 851 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 852 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 853 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 854 * @retval None 855 */ 856 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 857 858 /** 859 * @brief Enable Start the SD I/O Read Wait operation. 860 * @param __INSTANCE__ : Pointer to SDMMC register base 861 * @retval None 862 */ 863 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 864 865 /** 866 * @brief Disable Start the SD I/O Read Wait operations. 867 * @param __INSTANCE__ : Pointer to SDMMC register base 868 * @retval None 869 */ 870 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 871 872 /** 873 * @brief Enable Start the SD I/O Read Wait operation. 874 * @param __INSTANCE__ : Pointer to SDMMC register base 875 * @retval None 876 */ 877 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 878 879 /** 880 * @brief Disable Stop the SD I/O Read Wait operations. 881 * @param __INSTANCE__ : Pointer to SDMMC register base 882 * @retval None 883 */ 884 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 885 886 /** 887 * @brief Enable the SD I/O Mode Operation. 888 * @param __INSTANCE__ : Pointer to SDMMC register base 889 * @retval None 890 */ 891 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 892 893 /** 894 * @brief Disable the SD I/O Mode Operation. 895 * @param __INSTANCE__ : Pointer to SDMMC register base 896 * @retval None 897 */ 898 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 899 900 /** 901 * @brief Enable the SD I/O Suspend command sending. 902 * @param __INSTANCE__ : Pointer to SDMMC register base 903 * @retval None 904 */ 905 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 906 907 /** 908 * @brief Disable the SD I/O Suspend command sending. 909 * @param __INSTANCE__ : Pointer to SDMMC register base 910 * @retval None 911 */ 912 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 913 914 /** 915 * @} 916 */ 917 918 /** 919 * @} 920 */ 921 922 /* Exported functions --------------------------------------------------------*/ 923 /** @addtogroup SDMMC_LL_Exported_Functions 924 * @{ 925 */ 926 927 /* Initialization/de-initialization functions **********************************/ 928 /** @addtogroup HAL_SDMMC_LL_Group1 929 * @{ 930 */ 931 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 932 /** 933 * @} 934 */ 935 936 /* I/O operation functions *****************************************************/ 937 /** @addtogroup HAL_SDMMC_LL_Group2 938 * @{ 939 */ 940 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 941 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 942 /** 943 * @} 944 */ 945 946 /* Peripheral Control functions ************************************************/ 947 /** @addtogroup HAL_SDMMC_LL_Group3 948 * @{ 949 */ 950 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 951 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 952 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 953 954 /* Command path state machine (CPSM) management functions */ 955 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 956 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 957 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 958 959 /* Data path state machine (DPSM) management functions */ 960 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); 961 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 962 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 963 964 /* SDMMC Cards mode management functions */ 965 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 966 /** 967 * @} 968 */ 969 970 /* SDMMC Commands management functions */ 971 /** @addtogroup HAL_SDMMC_LL_Group4 972 * @{ 973 */ 974 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 975 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 976 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 977 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 978 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 979 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 980 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 981 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 982 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 983 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx); 984 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 985 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); 986 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 987 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 988 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 989 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 990 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 991 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 992 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 993 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 994 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 995 uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); 996 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 997 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 998 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 999 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1000 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1001 /** 1002 * @} 1003 */ 1004 1005 /* SDMMC Responses management functions *****************************************/ 1006 /** @addtogroup HAL_SDMMC_LL_Group5 1007 * @{ 1008 */ 1009 uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); 1010 uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); 1011 uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); 1012 uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); 1013 uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); 1014 /** 1015 * @} 1016 */ 1017 1018 /** 1019 * @} 1020 */ 1021 1022 /** 1023 * @} 1024 */ 1025 1026 /** 1027 * @} 1028 */ 1029 1030 #endif /* SDMMC1 */ 1031 1032 #ifdef __cplusplus 1033 } 1034 #endif 1035 1036 #endif /* STM32F7xx_LL_SDMMC_H */ 1037
