1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_LL_SDMMC_H 21 #define STM32MP1xx_LL_SDMMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_Driver 31 * @{ 32 */ 33 34 /** @addtogroup SDMMC_LL 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SDMMC Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 49 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 50 51 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 52 disabled when the bus is idle. 53 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 54 55 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 56 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 57 58 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 59 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 60 61 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 62 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ 63 64 }SDMMC_InitTypeDef; 65 66 67 /** 68 * @brief SDMMC Command Control structure 69 */ 70 typedef struct 71 { 72 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 73 to a card as part of a command message. If a command 74 contains an argument, it must be loaded into this register 75 before writing the command to the command register. */ 76 77 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 78 Max_Data = 64 */ 79 80 uint32_t Response; /*!< Specifies the SDMMC response type. 81 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 82 83 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 84 enabled or disabled. 85 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 86 87 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 88 is enabled or disabled. 89 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 90 }SDMMC_CmdInitTypeDef; 91 92 93 /** 94 * @brief SDMMC Data Control structure 95 */ 96 typedef struct 97 { 98 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 99 100 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 101 102 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 103 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 104 105 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 106 is a read or write. 107 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 108 109 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 110 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 111 112 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 113 is enabled or disabled. 114 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 115 }SDMMC_DataInitTypeDef; 116 117 /** 118 * @} 119 */ 120 121 /* Exported constants --------------------------------------------------------*/ 122 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 123 * @{ 124 */ 125 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 126 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 127 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 128 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 129 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 130 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 131 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 132 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 133 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the 134 number of transferred bytes does not match the block length */ 135 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 136 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 137 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 138 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock 139 command or if there was an attempt to access a locked card */ 140 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 141 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 142 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 143 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 144 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 145 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 146 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 147 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 148 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 149 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 150 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out 151 of erase sequence command was received */ 152 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 153 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 154 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 155 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 156 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 157 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 158 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 159 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 160 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 161 162 /** 163 * @brief SDMMC Commands Index 164 */ 165 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ 166 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ 167 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 168 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ 169 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ 170 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 171 operating condition register (OCR) content in the response on the CMD line. */ 172 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 173 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ 174 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 175 and asks the card whether card supports voltage. */ 176 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 177 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ 178 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ 179 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ 180 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ 181 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ 182 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ 183 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands 184 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 185 for SDHS and SDXC. */ 186 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 187 fixed 512 bytes in case of SDHC and SDXC. */ 188 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by 189 STOP_TRANSMISSION command. */ 190 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 191 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ 192 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ 193 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 194 fixed 512 bytes in case of SDHC and SDXC. */ 195 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 196 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ 197 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ 198 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ 199 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ 200 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ 201 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ 202 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ 203 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command 204 system set by switch function command (CMD6). */ 205 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. 206 Reserved for each command system set by switch function command (CMD6). */ 207 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ 208 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ 209 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ 210 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 211 the SET_BLOCK_LEN command. */ 212 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather 213 than a standard command. */ 214 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card 215 for general purpose/application specific commands. */ 216 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ 217 218 /** 219 * @brief Following commands are SD Card Specific commands. 220 * SDMMC_APP_CMD should be sent before sending these commands. 221 */ 222 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 223 widths are given in SCR register. */ 224 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ 225 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 226 32bit+CRC data block. */ 227 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 228 send its operating condition register (OCR) content in the response on the CMD line. */ 229 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 230 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ 231 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ 232 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ 233 234 /** 235 * @brief Following commands are SD Card Specific security commands. 236 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 237 */ 238 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) 239 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) 240 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) 241 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) 242 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) 243 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) 244 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) 245 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) 246 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) 247 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) 248 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) 249 250 /** 251 * @brief Masks for errors Card Status R1 (OCR Register) 252 */ 253 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 254 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 255 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 256 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 257 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 258 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 259 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 260 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 261 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 262 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 263 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 264 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 265 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 266 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 267 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 268 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 269 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 270 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 271 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 272 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 273 274 /** 275 * @brief Masks for R6 Response 276 */ 277 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 278 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 279 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 280 281 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 282 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 283 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 284 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 285 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 286 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) 287 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 288 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 289 290 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 291 292 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 293 294 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 295 296 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 297 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 298 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 299 300 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 301 302 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 303 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 304 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 305 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 306 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 307 308 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 309 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 310 311 /** 312 * @brief Command Class supported 313 */ 314 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 315 316 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 317 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 318 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 319 320 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 321 * @{ 322 */ 323 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 324 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 325 326 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 327 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 328 /** 329 * @} 330 */ 331 332 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 333 * @{ 334 */ 335 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 336 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 337 338 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 339 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 340 /** 341 * @} 342 */ 343 344 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 345 * @{ 346 */ 347 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 348 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 349 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 350 351 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 352 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 353 ((WIDE) == SDMMC_BUS_WIDE_8B)) 354 /** 355 * @} 356 */ 357 358 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 359 * @{ 360 */ 361 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 362 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 363 364 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 365 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 366 /** 367 * @} 368 */ 369 370 /** @defgroup SDMMC_LL_Clock_Division Clock Division 371 * @{ 372 */ 373 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 374 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 375 /** 376 * @} 377 */ 378 379 380 /** @defgroup SDMMC_LL_Command_Index Command Index 381 * @{ 382 */ 383 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 384 /** 385 * @} 386 */ 387 388 /** @defgroup SDMMC_LL_Response_Type Response Type 389 * @{ 390 */ 391 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 392 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 393 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 394 395 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 396 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 397 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 398 /** 399 * @} 400 */ 401 402 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 403 * @{ 404 */ 405 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 406 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 407 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 408 409 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 410 ((WAIT) == SDMMC_WAIT_IT) || \ 411 ((WAIT) == SDMMC_WAIT_PEND)) 412 /** 413 * @} 414 */ 415 416 /** @defgroup SDMMC_LL_CPSM_State CPSM State 417 * @{ 418 */ 419 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 420 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 421 422 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 423 ((CPSM) == SDMMC_CPSM_ENABLE)) 424 /** 425 * @} 426 */ 427 428 /** @defgroup SDMMC_LL_Response_Registers Response Register 429 * @{ 430 */ 431 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 432 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 433 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 434 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 435 436 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 437 ((RESP) == SDMMC_RESP2) || \ 438 ((RESP) == SDMMC_RESP3) || \ 439 ((RESP) == SDMMC_RESP4)) 440 441 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 442 * @{ 443 */ 444 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 445 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 446 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 447 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 448 449 /** 450 * @} 451 */ 452 453 /** @defgroup SDMMC_LL_Data_Length Data Lenght 454 * @{ 455 */ 456 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 457 /** 458 * @} 459 */ 460 461 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 462 * @{ 463 */ 464 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 465 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 466 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 467 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 468 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 469 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 470 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 471 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 472 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 473 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 474 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 475 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 476 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 477 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 478 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 479 480 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 481 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 482 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 483 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 484 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 485 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 486 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 487 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 488 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 489 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 490 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 491 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 492 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 493 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 494 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 495 /** 496 * @} 497 */ 498 499 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 500 * @{ 501 */ 502 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 503 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 504 505 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 506 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 507 /** 508 * @} 509 */ 510 511 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 512 * @{ 513 */ 514 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 515 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 516 517 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 518 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 519 /** 520 * @} 521 */ 522 523 /** @defgroup SDMMC_LL_DPSM_State DPSM State 524 * @{ 525 */ 526 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 527 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 528 529 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 530 ((DPSM) == SDMMC_DPSM_ENABLE)) 531 /** 532 * @} 533 */ 534 535 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 536 * @{ 537 */ 538 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 539 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 540 541 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 542 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 543 /** 544 * @} 545 */ 546 547 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 548 * @{ 549 */ 550 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 551 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 552 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 553 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 554 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 555 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 556 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 557 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 558 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 559 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 560 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 561 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 562 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 563 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 564 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 565 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 566 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 567 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 568 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 569 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 570 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 571 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 572 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 573 /** 574 * @} 575 */ 576 577 /** @defgroup SDMMC_LL_Flags Flags 578 * @{ 579 */ 580 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 581 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 582 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 583 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 584 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 585 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 586 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 587 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 588 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 589 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 590 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 591 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 592 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 593 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 594 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 595 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 596 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 597 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 598 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 599 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 600 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 601 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 602 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 603 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 604 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 605 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 606 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 607 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 608 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 609 610 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 611 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 612 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 613 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 614 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 615 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 616 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 617 618 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 619 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 620 621 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 622 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 623 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 624 SDMMC_FLAG_IDMABTC)) 625 /** 626 * @} 627 */ 628 629 /** 630 * @} 631 */ 632 633 /* Exported macro ------------------------------------------------------------*/ 634 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 635 * @{ 636 */ 637 638 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 639 * @brief SDMMC_LL registers bit address in the alias region 640 * @{ 641 */ 642 /* ---------------------- SDMMC registers bit mask --------------------------- */ 643 /* --- CLKCR Register ---*/ 644 /* CLKCR register clear mask */ 645 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 646 SDMMC_CLKCR_WIDBUS |\ 647 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 648 649 /* --- DCTRL Register ---*/ 650 /* SDMMC DCTRL Clear Mask */ 651 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 652 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 653 654 /* --- CMD Register ---*/ 655 /* CMD Register clear mask */ 656 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 657 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 658 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 659 660 /* SDMMC Initialization Frequency (400KHz max) for IP CLK 200MHz*/ 661 #define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA) 662 663 /* SDMMC Default Speed Frequency (25Mhz max) for IP CLK 200MHz*/ 664 #define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x4) 665 666 /* SDMMC High Speed Frequency (50Mhz max) for IP CLK 200MHz*/ 667 #define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2) 668 /** 669 * @} 670 */ 671 672 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 673 * @brief macros to handle interrupts and specific clock configurations 674 * @{ 675 */ 676 677 /** 678 * @brief Enable the SDMMC device interrupt. 679 * @param __INSTANCE__ : Pointer to SDMMC register base 680 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. 681 * This parameter can be one or a combination of the following values: 682 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 683 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 684 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 685 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 686 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 687 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 688 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 689 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 690 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 691 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 692 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 693 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 694 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 695 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 696 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 697 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 698 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 699 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 700 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 701 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 702 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 703 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 704 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 705 * @retval None 706 */ 707 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 708 709 /** 710 * @brief Disable the SDMMC device interrupt. 711 * @param __INSTANCE__ : Pointer to SDMMC register base 712 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. 713 * This parameter can be one or a combination of the following values: 714 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 715 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 716 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 717 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 718 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 719 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 720 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 721 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 722 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 723 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 724 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 725 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 726 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 727 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 728 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 729 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 730 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 731 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 732 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 733 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 734 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 735 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 736 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 737 * @retval None 738 */ 739 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 740 741 /** 742 * @brief Checks whether the specified SDMMC flag is set or not. 743 * @param __INSTANCE__ : Pointer to SDMMC register base 744 * @param __FLAG__: specifies the flag to check. 745 * This parameter can be one of the following values: 746 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 747 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 748 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 749 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 750 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 751 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 752 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 753 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 754 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 755 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 756 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 757 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 758 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 759 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 760 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 761 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 762 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 763 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 764 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 765 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 766 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 767 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 768 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 769 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 770 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 771 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 772 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 773 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 774 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 775 * @retval The new state of SDMMC_FLAG (SET or RESET). 776 */ 777 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 778 779 780 /** 781 * @brief Clears the SDMMC pending flags. 782 * @param __INSTANCE__ : Pointer to SDMMC register base 783 * @param __FLAG__: specifies the flag to clear. 784 * This parameter can be one or a combination of the following values: 785 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 786 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 787 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 788 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 789 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 790 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 791 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 792 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 793 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 794 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 795 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 796 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 797 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 798 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 799 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 800 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 801 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 802 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 803 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 804 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 805 * @retval None 806 */ 807 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 808 809 /** 810 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 811 * @param __INSTANCE__ : Pointer to SDMMC register base 812 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. 813 * This parameter can be one of the following values: 814 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 815 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 816 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 817 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 818 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 819 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 820 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 821 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 822 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 823 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 824 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 825 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 826 * @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt 827 * @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt 828 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 829 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 830 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 831 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 832 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 833 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 834 * @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 835 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 836 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 837 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 838 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 839 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 840 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 841 * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt 842 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 843 * @retval The new state of SDMMC_IT (SET or RESET). 844 */ 845 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 846 847 /** 848 * @brief Clears the SDMMC's interrupt pending bits. 849 * @param __INSTANCE__ : Pointer to SDMMC register base 850 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 851 * This parameter can be one or a combination of the following values: 852 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 853 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 854 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 855 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 856 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 857 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 858 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 859 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 860 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 861 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 862 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 863 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 864 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 865 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 866 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 867 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 868 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 869 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 870 * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt 871 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 872 * @retval None 873 */ 874 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 875 876 /** 877 * @brief Enable Start the SD I/O Read Wait operation. 878 * @param __INSTANCE__ : Pointer to SDMMC register base 879 * @retval None 880 */ 881 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 882 883 /** 884 * @brief Disable Start the SD I/O Read Wait operations. 885 * @param __INSTANCE__ : Pointer to SDMMC register base 886 * @retval None 887 */ 888 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 889 890 /** 891 * @brief Enable Start the SD I/O Read Wait operation. 892 * @param __INSTANCE__ : Pointer to SDMMC register base 893 * @retval None 894 */ 895 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 896 897 /** 898 * @brief Disable Stop the SD I/O Read Wait operations. 899 * @param __INSTANCE__ : Pointer to SDMMC register base 900 * @retval None 901 */ 902 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 903 904 /** 905 * @brief Enable the SD I/O Mode Operation. 906 * @param __INSTANCE__ : Pointer to SDMMC register base 907 * @retval None 908 */ 909 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 910 911 /** 912 * @brief Disable the SD I/O Mode Operation. 913 * @param __INSTANCE__ : Pointer to SDMMC register base 914 * @retval None 915 */ 916 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 917 918 /** 919 * @brief Enable the SD I/O Suspend command sending. 920 * @param __INSTANCE__ : Pointer to SDMMC register base 921 * @retval None 922 */ 923 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 924 925 /** 926 * @brief Disable the SD I/O Suspend command sending. 927 * @param __INSTANCE__ : Pointer to SDMMC register base 928 * @retval None 929 */ 930 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 931 932 /** 933 * @brief Enable the CMDTRANS mode. 934 * @param __INSTANCE__ : Pointer to SDMMC register base 935 * @retval None 936 */ 937 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 938 939 /** 940 * @brief Disable the CMDTRANS mode. 941 * @param __INSTANCE__ : Pointer to SDMMC register base 942 * @retval None 943 */ 944 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 945 946 /** 947 * @brief Enable the CMDSTOP mode. 948 * @param __INSTANCE__ : Pointer to SDMMC register base 949 * @retval None 950 */ 951 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) 952 953 /** 954 * @brief Disable the CMDSTOP mode. 955 * @param __INSTANCE__ : Pointer to SDMMC register base 956 * @retval None 957 */ 958 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) 959 960 /** 961 * @} 962 */ 963 964 /** 965 * @} 966 */ 967 968 /* Exported functions --------------------------------------------------------*/ 969 /** @addtogroup SDMMC_LL_Exported_Functions 970 * @{ 971 */ 972 973 /* Initialization/de-initialization functions **********************************/ 974 /** @addtogroup HAL_SDMMC_LL_Group1 975 * @{ 976 */ 977 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 978 /** 979 * @} 980 */ 981 982 /* I/O operation functions *****************************************************/ 983 /** @addtogroup HAL_SDMMC_LL_Group2 984 * @{ 985 */ 986 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 987 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 988 /** 989 * @} 990 */ 991 992 /* Peripheral Control functions ************************************************/ 993 /** @addtogroup HAL_SDMMC_LL_Group3 994 * @{ 995 */ 996 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 997 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 998 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 999 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 1000 1001 /* Command path state machine (CPSM) management functions */ 1002 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 1003 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 1004 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 1005 1006 /* Data path state machine (DPSM) management functions */ 1007 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); 1008 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 1009 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 1010 1011 /* SDMMC Cards mode management functions */ 1012 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1013 1014 /* SDMMC Commands management functions */ 1015 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1016 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1017 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1018 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1019 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1020 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1021 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1022 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1023 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1024 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx); 1025 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1026 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); 1027 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1028 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1029 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1030 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1031 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1032 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1033 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1034 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1035 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1036 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1037 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1038 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1039 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1040 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1041 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1042 1043 /** 1044 * @} 1045 */ 1046 1047 /** 1048 * @} 1049 */ 1050 1051 /** 1052 * @} 1053 */ 1054 1055 /** 1056 * @} 1057 */ 1058 1059 /** 1060 * @} 1061 */ 1062 1063 /** 1064 * @} 1065 */ 1066 #ifdef __cplusplus 1067 } 1068 #endif 1069 1070 #endif /* STM32MP1xx_LL_SDMMC_H */ 1071
