1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_LL_SDMMC_H 21 #define STM32L5xx_LL_SDMMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l5xx_hal_def.h" 29 30 /** @addtogroup STM32L5xx_Driver 31 * @{ 32 */ 33 34 /** @addtogroup SDMMC_LL 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SDMMC Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change. 49 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 50 51 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 52 disabled when the bus is idle. 53 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 54 55 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 56 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 57 58 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 59 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 60 61 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 62 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ 63 64 #if (USE_SD_TRANSCEIVER != 0U) 65 uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. 66 This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ 67 #endif /* USE_SD_TRANSCEIVER */ 68 } SDMMC_InitTypeDef; 69 70 71 /** 72 * @brief SDMMC Command Control structure 73 */ 74 typedef struct 75 { 76 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 77 to a card as part of a command message. If a command 78 contains an argument, it must be loaded into this register 79 before writing the command to the command register. */ 80 81 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 82 Max_Data = 64 */ 83 84 uint32_t Response; /*!< Specifies the SDMMC response type. 85 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 86 87 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 88 enabled or disabled. 89 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 90 91 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 92 is enabled or disabled. 93 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 94 } SDMMC_CmdInitTypeDef; 95 96 97 /** 98 * @brief SDMMC Data Control structure 99 */ 100 typedef struct 101 { 102 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 103 104 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 105 106 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 107 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 108 109 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 110 is a read or write. 111 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 112 113 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 114 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 115 116 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 117 is enabled or disabled. 118 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 119 } SDMMC_DataInitTypeDef; 120 121 /** 122 * @} 123 */ 124 125 /* Exported constants --------------------------------------------------------*/ 126 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 127 * @{ 128 */ 129 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 130 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 131 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 132 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 133 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 134 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 135 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 136 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 137 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ 138 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 139 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 140 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 141 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ 142 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 143 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 144 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 145 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 146 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 147 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 148 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 149 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 150 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 151 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 152 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ 153 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 154 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 155 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 156 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 157 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 158 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 159 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 160 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 161 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 162 163 /** 164 * @brief SDMMC Commands Index 165 */ 166 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ 167 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ 168 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 169 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ 170 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ 171 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ 172 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 173 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ 174 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ 175 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 176 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ 177 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ 178 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ 179 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ 180 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ 181 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ 182 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ 183 /*!< for SDHS and SDXC. */ 184 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 185 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ 186 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 187 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ 188 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ 189 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ 190 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 191 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ 192 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ 193 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ 194 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ 195 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ 196 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ 197 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ 198 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ 199 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ 200 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ 201 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ 202 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ 203 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ 204 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ 205 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ 206 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ 207 208 /** 209 * @brief Following commands are SD Card Specific commands. 210 * SDMMC_APP_CMD should be sent before sending these commands. 211 */ 212 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ 213 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ 214 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ 215 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ 216 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 217 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ 218 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ 219 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ 220 221 /** 222 * @brief Following commands are MMC Specific commands. 223 */ 224 #define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ 225 226 /** 227 * @brief Following commands are SD Card Specific security commands. 228 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 229 */ 230 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) 231 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) 232 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) 233 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) 234 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) 235 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) 236 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) 237 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) 238 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) 239 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) 240 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) 241 242 /** 243 * @brief Masks for errors Card Status R1 (OCR Register) 244 */ 245 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 246 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 247 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 248 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 249 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 250 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 251 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 252 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 253 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 254 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 255 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 256 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 257 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 258 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 259 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 260 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 261 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 262 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 263 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 264 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 265 266 /** 267 * @brief Masks for R6 Response 268 */ 269 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 270 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 271 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 272 273 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 274 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 275 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 276 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 277 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 278 #define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U) 279 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) 280 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 281 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 282 283 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 284 285 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 286 287 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 288 289 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 290 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 291 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 292 293 #ifndef SDMMC_DATATIMEOUT 294 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 295 #endif /* SDMMC_DATATIMEOUT */ 296 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 297 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 298 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 299 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 300 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 301 302 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 303 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 304 305 /** 306 * @brief Command Class supported 307 */ 308 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 309 310 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 311 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 312 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 313 314 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 315 * @{ 316 */ 317 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 318 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 319 320 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 321 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 322 /** 323 * @} 324 */ 325 326 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 327 * @{ 328 */ 329 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 330 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 331 332 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 333 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 334 /** 335 * @} 336 */ 337 338 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 339 * @{ 340 */ 341 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 342 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 343 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 344 345 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 346 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 347 ((WIDE) == SDMMC_BUS_WIDE_8B)) 348 /** 349 * @} 350 */ 351 352 /** @defgroup SDMMC_LL_Speed_Mode 353 * @{ 354 */ 355 #define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U) 356 #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) 357 #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) 358 #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) 359 #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) 360 361 #define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ 362 ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ 363 ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ 364 ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ 365 ((MODE) == SDMMC_SPEED_MODE_DDR)) 366 367 /** 368 * @} 369 */ 370 371 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 372 * @{ 373 */ 374 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 375 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 376 377 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 378 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 379 /** 380 * @} 381 */ 382 383 /** @defgroup SDMMC_LL_Clock_Division Clock Division 384 * @{ 385 */ 386 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 387 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 388 /** 389 * @} 390 */ 391 392 /** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present 393 * @{ 394 */ 395 #define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U) 396 #define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U) 397 #define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U) 398 399 /** 400 * @} 401 */ 402 403 /** @defgroup SDMMC_LL_Command_Index Command Index 404 * @{ 405 */ 406 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 407 /** 408 * @} 409 */ 410 411 /** @defgroup SDMMC_LL_Response_Type Response Type 412 * @{ 413 */ 414 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 415 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 416 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 417 418 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 419 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 420 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 421 /** 422 * @} 423 */ 424 425 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 426 * @{ 427 */ 428 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 429 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 430 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 431 432 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 433 ((WAIT) == SDMMC_WAIT_IT) || \ 434 ((WAIT) == SDMMC_WAIT_PEND)) 435 /** 436 * @} 437 */ 438 439 /** @defgroup SDMMC_LL_CPSM_State CPSM State 440 * @{ 441 */ 442 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 443 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 444 445 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 446 ((CPSM) == SDMMC_CPSM_ENABLE)) 447 /** 448 * @} 449 */ 450 451 /** @defgroup SDMMC_LL_Response_Registers Response Register 452 * @{ 453 */ 454 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 455 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 456 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 457 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 458 459 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 460 ((RESP) == SDMMC_RESP2) || \ 461 ((RESP) == SDMMC_RESP3) || \ 462 ((RESP) == SDMMC_RESP4)) 463 464 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 465 * @{ 466 */ 467 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 468 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 469 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 470 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 471 472 /** 473 * @} 474 */ 475 476 /** @defgroup SDMMC_LL_Data_Length Data Length 477 * @{ 478 */ 479 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 480 /** 481 * @} 482 */ 483 484 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 485 * @{ 486 */ 487 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 488 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 489 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 490 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 491 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 492 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 493 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 494 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 495 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 496 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 497 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 498 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 499 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 500 SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 501 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 502 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \ 503 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 504 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \ 505 SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 506 507 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 508 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 509 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 510 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 511 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 512 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 513 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 514 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 515 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 516 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 517 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 518 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 519 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 520 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 521 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 522 /** 523 * @} 524 */ 525 526 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 527 * @{ 528 */ 529 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 530 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 531 532 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 533 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 534 /** 535 * @} 536 */ 537 538 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 539 * @{ 540 */ 541 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 542 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 543 544 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 545 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 546 /** 547 * @} 548 */ 549 550 /** @defgroup SDMMC_LL_DPSM_State DPSM State 551 * @{ 552 */ 553 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 554 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 555 556 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 557 ((DPSM) == SDMMC_DPSM_ENABLE)) 558 /** 559 * @} 560 */ 561 562 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 563 * @{ 564 */ 565 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 566 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 567 568 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 569 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 570 /** 571 * @} 572 */ 573 574 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 575 * @{ 576 */ 577 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 578 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 579 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 580 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 581 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 582 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 583 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 584 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 585 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 586 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 587 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 588 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 589 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 590 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 591 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 592 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 593 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 594 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 595 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 596 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 597 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 598 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 599 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 600 /** 601 * @} 602 */ 603 604 /** @defgroup SDMMC_LL_Flags Flags 605 * @{ 606 */ 607 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 608 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 609 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 610 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 611 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 612 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 613 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 614 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 615 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 616 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 617 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 618 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 619 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 620 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 621 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 622 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 623 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 624 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 625 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 626 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 627 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 628 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 629 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 630 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 631 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 632 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 633 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 634 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 635 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 636 637 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 638 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 639 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 640 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 641 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 642 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 643 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 644 645 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 646 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 647 648 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 649 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 650 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 651 SDMMC_FLAG_IDMABTC)) 652 /** 653 * @} 654 */ 655 656 /** 657 * @} 658 */ 659 660 /* Exported macro ------------------------------------------------------------*/ 661 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 662 * @{ 663 */ 664 665 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 666 * @brief SDMMC_LL registers bit address in the alias region 667 * @{ 668 */ 669 /* ---------------------- SDMMC registers bit mask --------------------------- */ 670 /* --- CLKCR Register ---*/ 671 /* CLKCR register clear mask */ 672 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 673 SDMMC_CLKCR_WIDBUS |\ 674 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\ 675 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\ 676 SDMMC_CLKCR_SELCLKRX)) 677 678 /* --- DCTRL Register ---*/ 679 /* SDMMC DCTRL Clear Mask */ 680 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 681 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 682 683 /* --- CMD Register ---*/ 684 /* CMD Register clear mask */ 685 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 686 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 687 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 688 689 /* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 110MHz*/ 690 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x8A) 691 692 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 110MHz*/ 693 #define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x3) 694 695 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 110MHz*/ 696 #define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2) 697 /** 698 * @} 699 */ 700 701 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 702 * @brief macros to handle interrupts and specific clock configurations 703 * @{ 704 */ 705 706 /** 707 * @brief Enable the SDMMC device interrupt. 708 * @param __INSTANCE__ Pointer to SDMMC register base 709 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. 710 * This parameter can be one or a combination of the following values: 711 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 712 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 713 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 714 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 715 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 716 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 717 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 718 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 719 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 720 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 721 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 722 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 723 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 724 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 725 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 726 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 727 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 728 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 729 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 730 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 731 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 732 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 733 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 734 * @retval None 735 */ 736 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 737 738 /** 739 * @brief Disable the SDMMC device interrupt. 740 * @param __INSTANCE__ Pointer to SDMMC register base 741 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. 742 * This parameter can be one or a combination of the following values: 743 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 744 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 745 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 746 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 747 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 748 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 749 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 750 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 751 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 752 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 753 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 754 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 755 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 756 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 757 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 758 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 759 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 760 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 761 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 762 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 763 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 764 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 765 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 766 * @retval None 767 */ 768 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 769 770 /** 771 * @brief Checks whether the specified SDMMC flag is set or not. 772 * @param __INSTANCE__ Pointer to SDMMC register base 773 * @param __FLAG__ specifies the flag to check. 774 * This parameter can be one of the following values: 775 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 776 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 777 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 778 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 779 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 780 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 781 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 782 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 783 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 784 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 785 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 786 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 787 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 788 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 789 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 790 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 791 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 792 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 793 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 794 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 795 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 796 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 797 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 798 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 799 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 800 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 801 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 802 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 803 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 804 * @retval The new state of SDMMC_FLAG (SET or RESET). 805 */ 806 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 807 808 809 /** 810 * @brief Clears the SDMMC pending flags. 811 * @param __INSTANCE__ Pointer to SDMMC register base 812 * @param __FLAG__ specifies the flag to clear. 813 * This parameter can be one or a combination of the following values: 814 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 815 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 816 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 817 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 818 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 819 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 820 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 821 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 822 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 823 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 824 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 825 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 826 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 827 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 828 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 829 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 830 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 831 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 832 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 833 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 834 * @retval None 835 */ 836 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 837 838 /** 839 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 840 * @param __INSTANCE__ Pointer to SDMMC register base 841 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 842 * This parameter can be one of the following values: 843 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 844 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 845 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 846 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 847 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 848 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 849 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 850 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 851 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 852 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 853 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 854 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 855 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 856 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 857 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 858 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 859 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 860 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 861 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 862 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 863 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 864 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 865 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 866 * @retval The new state of SDMMC_IT (SET or RESET). 867 */ 868 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 869 870 /** 871 * @brief Clears the SDMMC's interrupt pending bits. 872 * @param __INSTANCE__ Pointer to SDMMC register base 873 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 874 * This parameter can be one or a combination of the following values: 875 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 876 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 877 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 878 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 879 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 880 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 881 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 882 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 883 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 884 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 885 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 886 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 887 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 888 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 889 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 890 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 891 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 892 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 893 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 894 * @retval None 895 */ 896 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 897 898 /** 899 * @brief Enable Start the SD I/O Read Wait operation. 900 * @param __INSTANCE__ Pointer to SDMMC register base 901 * @retval None 902 */ 903 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 904 905 /** 906 * @brief Disable Start the SD I/O Read Wait operations. 907 * @param __INSTANCE__ Pointer to SDMMC register base 908 * @retval None 909 */ 910 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 911 912 /** 913 * @brief Enable Start the SD I/O Read Wait operation. 914 * @param __INSTANCE__ Pointer to SDMMC register base 915 * @retval None 916 */ 917 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 918 919 /** 920 * @brief Disable Stop the SD I/O Read Wait operations. 921 * @param __INSTANCE__ Pointer to SDMMC register base 922 * @retval None 923 */ 924 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 925 926 /** 927 * @brief Enable the SD I/O Mode Operation. 928 * @param __INSTANCE__ Pointer to SDMMC register base 929 * @retval None 930 */ 931 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 932 933 /** 934 * @brief Disable the SD I/O Mode Operation. 935 * @param __INSTANCE__ Pointer to SDMMC register base 936 * @retval None 937 */ 938 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 939 940 /** 941 * @brief Enable the SD I/O Suspend command sending. 942 * @param __INSTANCE__ Pointer to SDMMC register base 943 * @retval None 944 */ 945 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 946 947 /** 948 * @brief Disable the SD I/O Suspend command sending. 949 * @param __INSTANCE__ Pointer to SDMMC register base 950 * @retval None 951 */ 952 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 953 954 /** 955 * @brief Enable the CMDTRANS mode. 956 * @param __INSTANCE__ Pointer to SDMMC register base 957 * @retval None 958 */ 959 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 960 961 /** 962 * @brief Disable the CMDTRANS mode. 963 * @param __INSTANCE__ Pointer to SDMMC register base 964 * @retval None 965 */ 966 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 967 968 /** 969 * @brief Enable the CMDSTOP mode. 970 * @param __INSTANCE__ Pointer to SDMMC register base 971 * @retval None 972 */ 973 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) 974 975 /** 976 * @brief Disable the CMDSTOP mode. 977 * @param __INSTANCE__ Pointer to SDMMC register base 978 * @retval None 979 */ 980 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) 981 982 /** 983 * @} 984 */ 985 986 /** 987 * @} 988 */ 989 990 /* Exported functions --------------------------------------------------------*/ 991 /** @addtogroup SDMMC_LL_Exported_Functions 992 * @{ 993 */ 994 995 /* Initialization/de-initialization functions **********************************/ 996 /** @addtogroup HAL_SDMMC_LL_Group1 997 * @{ 998 */ 999 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 1000 /** 1001 * @} 1002 */ 1003 1004 /* I/O operation functions *****************************************************/ 1005 /** @addtogroup HAL_SDMMC_LL_Group2 1006 * @{ 1007 */ 1008 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 1009 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 1010 /** 1011 * @} 1012 */ 1013 1014 /* Peripheral Control functions ************************************************/ 1015 /** @addtogroup HAL_SDMMC_LL_Group3 1016 * @{ 1017 */ 1018 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 1019 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 1020 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 1021 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 1022 1023 /* Command path state machine (CPSM) management functions */ 1024 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 1025 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 1026 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 1027 1028 /* Data path state machine (DPSM) management functions */ 1029 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); 1030 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 1031 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 1032 1033 /* SDMMC Cards mode management functions */ 1034 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1035 /** 1036 * @} 1037 */ 1038 1039 /* SDMMC Commands management functions ******************************************/ 1040 /** @addtogroup HAL_SDMMC_LL_Group4 1041 * @{ 1042 */ 1043 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1044 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1045 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1046 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1047 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1048 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1049 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1050 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1051 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1052 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); 1053 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1054 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr); 1055 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1056 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1057 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1058 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1059 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1060 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1061 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1062 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1063 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1064 uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); 1065 uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1066 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1067 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1068 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1069 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1070 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1071 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1072 /** 1073 * @} 1074 */ 1075 1076 /* SDMMC Responses management functions *****************************************/ 1077 /** @addtogroup HAL_SDMMC_LL_Group5 1078 * @{ 1079 */ 1080 uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); 1081 uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); 1082 uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); 1083 uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); 1084 uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); 1085 /** 1086 * @} 1087 */ 1088 1089 1090 /** 1091 * @} 1092 */ 1093 1094 /** 1095 * @} 1096 */ 1097 1098 /** 1099 * @} 1100 */ 1101 1102 /** 1103 * @} 1104 */ 1105 1106 /** 1107 * @} 1108 */ 1109 #ifdef __cplusplus 1110 } 1111 #endif 1112 1113 #endif /* STM32L5xx_LL_SDMMC_H */ 1114
