| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
19 (((((reg)&CGC_SOSCDIV_DIV1_MASK) >> CGC_SOSCDIV_DIV1_SHIFT) + 1U) * \
20 ((((reg)&CGC_SOSCDIV_DIV1HALT_MASK) >> CGC_SOSCDIV_DIV1HALT_SHIFT) ^ 1U))
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
22 (((((reg)&CGC_SOSCDIV_DIV2_MASK) >> CGC_SOSCDIV_DIV2_SHIFT) + 1U) * \
23 ((((reg)&CGC_SOSCDIV_DIV2HALT_MASK) >> CGC_SOSCDIV_DIV2HALT_SHIFT) ^ 1U))
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
25 (((((reg)&CGC_SOSCDIV_DIV3_MASK) >> CGC_SOSCDIV_DIV3_SHIFT) + 1U) * \
26 ((((reg)&CGC_SOSCDIV_DIV3HALT_MASK) >> CGC_SOSCDIV_DIV3HALT_SHIFT) ^ 1U))
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
19 (((((reg)&CGC_SOSCDIV_DIV1_MASK) >> CGC_SOSCDIV_DIV1_SHIFT) + 1U) * \
20 ((((reg)&CGC_SOSCDIV_DIV1HALT_MASK) >> CGC_SOSCDIV_DIV1HALT_SHIFT) ^ 1U))
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
22 (((((reg)&CGC_SOSCDIV_DIV2_MASK) >> CGC_SOSCDIV_DIV2_SHIFT) + 1U) * \
23 ((((reg)&CGC_SOSCDIV_DIV2HALT_MASK) >> CGC_SOSCDIV_DIV2HALT_SHIFT) ^ 1U))
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
25 (((((reg)&CGC_SOSCDIV_DIV3_MASK) >> CGC_SOSCDIV_DIV3_SHIFT) + 1U) * \
26 ((((reg)&CGC_SOSCDIV_DIV3HALT_MASK) >> CGC_SOSCDIV_DIV3HALT_SHIFT) ^ 1U))
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
19 (((((reg)&CGC_SOSCDIV_DIV1_MASK) >> CGC_SOSCDIV_DIV1_SHIFT) + 1U) * \
20 ((((reg)&CGC_SOSCDIV_DIV1HALT_MASK) >> CGC_SOSCDIV_DIV1HALT_SHIFT) ^ 1U))
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
22 (((((reg)&CGC_SOSCDIV_DIV2_MASK) >> CGC_SOSCDIV_DIV2_SHIFT) + 1U) * \
23 ((((reg)&CGC_SOSCDIV_DIV2HALT_MASK) >> CGC_SOSCDIV_DIV2HALT_SHIFT) ^ 1U))
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
25 (((((reg)&CGC_SOSCDIV_DIV3_MASK) >> CGC_SOSCDIV_DIV3_SHIFT) + 1U) * \
26 ((((reg)&CGC_SOSCDIV_DIV3HALT_MASK) >> CGC_SOSCDIV_DIV3HALT_SHIFT) ^ 1U))
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
19 (((((reg)&CGC_SOSCDIV_DIV1_MASK) >> CGC_SOSCDIV_DIV1_SHIFT) + 1U) * \
20 ((((reg)&CGC_SOSCDIV_DIV1HALT_MASK) >> CGC_SOSCDIV_DIV1HALT_SHIFT) ^ 1U))
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
22 (((((reg)&CGC_SOSCDIV_DIV2_MASK) >> CGC_SOSCDIV_DIV2_SHIFT) + 1U) * \
23 ((((reg)&CGC_SOSCDIV_DIV2HALT_MASK) >> CGC_SOSCDIV_DIV2HALT_SHIFT) ^ 1U))
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
25 (((((reg)&CGC_SOSCDIV_DIV3_MASK) >> CGC_SOSCDIV_DIV3_SHIFT) + 1U) * \
26 ((((reg)&CGC_SOSCDIV_DIV3HALT_MASK) >> CGC_SOSCDIV_DIV3HALT_SHIFT) ^ 1U))
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
19 (((((reg)&CGC_SOSCDIV_DIV1_MASK) >> CGC_SOSCDIV_DIV1_SHIFT) + 1U) * \
20 ((((reg)&CGC_SOSCDIV_DIV1HALT_MASK) >> CGC_SOSCDIV_DIV1HALT_SHIFT) ^ 1U))
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
22 (((((reg)&CGC_SOSCDIV_DIV2_MASK) >> CGC_SOSCDIV_DIV2_SHIFT) + 1U) * \
23 ((((reg)&CGC_SOSCDIV_DIV2HALT_MASK) >> CGC_SOSCDIV_DIV2HALT_SHIFT) ^ 1U))
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
25 (((((reg)&CGC_SOSCDIV_DIV3_MASK) >> CGC_SOSCDIV_DIV3_SHIFT) + 1U) * \
26 ((((reg)&CGC_SOSCDIV_DIV3HALT_MASK) >> CGC_SOSCDIV_DIV3HALT_SHIFT) ^ 1U))
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/qtmr_1/ |
| D | fsl_qtmr.c | 175 uint16_t reg; in QTMR_SetupPwm() local
211 reg = base->CHANNEL[channel].CSCTRL; in QTMR_SetupPwm()
215 reg &= (uint16_t)(~(TMR_CSCTRL_CL1_MASK | TMR_CSCTRL_CL2_MASK)); in QTMR_SetupPwm()
216 reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1)); in QTMR_SetupPwm()
217 base->CHANNEL[channel].CSCTRL = reg; in QTMR_SetupPwm()
230 reg = base->CHANNEL[channel].CTRL; in QTMR_SetupPwm()
231 reg &= ~(uint16_t)TMR_CTRL_OUTMODE_MASK; in QTMR_SetupPwm()
235 reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_SetOnCompare)); in QTMR_SetupPwm()
240 reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ClearOnCompare)); in QTMR_SetupPwm()
245 reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg)); in QTMR_SetupPwm()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/smc/ |
| D | fsl_smc.c | 92 uint32_t reg = base->PARAM; in SMC_GetParam() local
93 param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); in SMC_GetParam()
94 param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); in SMC_GetParam()
95 param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); in SMC_GetParam()
96 param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); in SMC_GetParam()
154 smc_reg_t reg; in SMC_SetPowerModeRun() local
156 reg = base->PMCTRL; in SMC_SetPowerModeRun()
158 reg &= ~(smc_reg_t)SMC_PMCTRL_RUNM_MASK; in SMC_SetPowerModeRun()
159 reg |= ((smc_reg_t)kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); in SMC_SetPowerModeRun()
160 base->PMCTRL = reg; in SMC_SetPowerModeRun()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/qtmr_2/ |
| D | fsl_qtmr.c | 163 uint16_t reg; in QTMR_SetupPwm() local
184 reg = base->CSCTRL; in QTMR_SetupPwm()
188 reg &= ~((uint16_t)TMR_CSCTRL_CL1_MASK | (uint16_t)TMR_CSCTRL_CL2_MASK); in QTMR_SetupPwm()
189 reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1)); in QTMR_SetupPwm()
190 base->CSCTRL = reg; in QTMR_SetupPwm()
203 reg = base->CTRL; in QTMR_SetupPwm()
204 reg &= ~(uint16_t)TMR_CTRL_OUTMODE_MASK; in QTMR_SetupPwm()
208 reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg)); in QTMR_SetupPwm()
209 base->CTRL = reg; in QTMR_SetupPwm()
237 uint16_t reg; in QTMR_SetupInputCapture() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/ftm/ |
| D | fsl_ftm.c | 96 uint32_t reg = 0, syncReg = 0; in FTM_SetPwmSync() local
105 reg = base->COMBINE; in FTM_SetPwmSync()
109 reg |= (1UL << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber))); in FTM_SetPwmSync()
111 base->COMBINE = reg; in FTM_SetPwmSync()
113 reg = base->SYNCONF; in FTM_SetPwmSync()
116 …reg |= (FTM_SYNCONF_SYNCMODE_MASK | FTM_SYNCONF_CNTINC_MASK | FTM_SYNCONF_INVC_MASK | FTM_SYNCONF_… in FTM_SetPwmSync()
121 …reg |= (FTM_SYNCONF_SWWRBUF_MASK | FTM_SYNCONF_SWINVC_MASK | FTM_SYNCONF_SWSOC_MASK | FTM_SYNCONF_… in FTM_SetPwmSync()
125 reg |= FTM_SYNCONF_SWRSTCNT_MASK; in FTM_SetPwmSync()
132 …reg |= (FTM_SYNCONF_HWWRBUF_MASK | FTM_SYNCONF_HWINVC_MASK | FTM_SYNCONF_HWSOC_MASK | FTM_SYNCONF_… in FTM_SetPwmSync()
136 reg |= FTM_SYNCONF_HWRSTCNT_MASK; in FTM_SetPwmSync()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/msmc/ |
| D | fsl_msmc.c | 24 uint32_t reg; in SMC_SetPowerModeRun() local
26 reg = base->PMCTRL; in SMC_SetPowerModeRun()
28 reg &= ~SMC_PMCTRL_RUNM_MASK; in SMC_SetPowerModeRun()
29 reg |= ((uint32_t)kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); in SMC_SetPowerModeRun()
30 base->PMCTRL = reg; in SMC_SetPowerModeRun()
43 uint32_t reg; in SMC_SetPowerModeHsrun() local
45 reg = base->PMCTRL; in SMC_SetPowerModeHsrun()
47 reg &= ~SMC_PMCTRL_RUNM_MASK; in SMC_SetPowerModeHsrun()
48 reg |= ((uint32_t)kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); in SMC_SetPowerModeHsrun()
49 base->PMCTRL = reg; in SMC_SetPowerModeHsrun()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/asmc/ |
| D | fsl_asmc.c | 24 uint32_t reg; in ASMC_SetPowerModeRun() local
26 reg = base->PMCTRL; in ASMC_SetPowerModeRun()
28 reg &= ~ASMC_PMCTRL_RUNM_MASK; in ASMC_SetPowerModeRun()
29 reg |= ((uint32_t)kASMC_RunNormal << ASMC_PMCTRL_RUNM_SHIFT); in ASMC_SetPowerModeRun()
30 base->PMCTRL = reg; in ASMC_SetPowerModeRun()
44 uint32_t reg; in ASMC_SetPowerModeHsrun() local
46 reg = base->PMCTRL; in ASMC_SetPowerModeHsrun()
48 reg &= ~ASMC_PMCTRL_RUNM_MASK; in ASMC_SetPowerModeHsrun()
49 reg |= (kASMC_Hsrun << ASMC_PMCTRL_RUNM_SHIFT); in ASMC_SetPowerModeHsrun()
50 base->PMCTRL = reg; in ASMC_SetPowerModeHsrun()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/spc/ |
| D | fsl_spc.c | 66 uint32_t reg; in SPC_GetPeriphIOIsolationStatus() local
68 reg = base->SC; in SPC_GetPeriphIOIsolationStatus()
69 return (uint8_t)((reg & SPC_SC_ISO_CLR_MASK) >> SPC_SC_ISO_CLR_SHIFT); in SPC_GetPeriphIOIsolationStatus()
84 uint32_t reg; in SPC_SetLowPowerRequestConfig() local
86 reg = base->LPREQ_CFG; in SPC_SetLowPowerRequestConfig()
87 reg &= ~(SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL_MASK | SPC_LPREQ_CFG_LPREQOV_MASK); in SPC_SetLowPowerRequestConfig()
91 reg |= SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL((uint8_t)(config->polarity)) | in SPC_SetLowPowerRequestConfig()
96 reg &= ~SPC_LPREQ_CFG_LPREQOE_MASK; in SPC_SetLowPowerRequestConfig()
99 base->LPREQ_CFG = reg; in SPC_SetLowPowerRequestConfig()
148 uint32_t reg; in SPC_SetActiveModeBandgapModeConfig() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/cmc/ |
| D | fsl_cmc.c | 49 uint32_t reg; in CMC_SetClockMode() local
51 reg = base->CKCTRL; in CMC_SetClockMode()
52 reg &= ~CMC_CKCTRL_CKMODE_MASK; in CMC_SetClockMode()
53 reg |= CMC_CKCTRL_CKMODE((mode)); in CMC_SetClockMode()
54 base->CKCTRL = reg; in CMC_SetClockMode()
73 uint32_t reg; in CMC_SetPowerModeProtection() local
75 reg = base->PMPROT; in CMC_SetPowerModeProtection()
76 reg &= ~0xFUL; in CMC_SetPowerModeProtection()
77 reg |= allowedModes; in CMC_SetPowerModeProtection()
79 base->PMPROT = reg; in CMC_SetPowerModeProtection()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/drivers/ |
| D | fsl_clock.h | 688 uint32_t reg = (*(volatile uint32_t *)(uint32_t)name); in CLOCK_SetIpSrc() local
690 assert((reg & PCC_CLKCFG_PR_MASK) != 0UL); in CLOCK_SetIpSrc()
691 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrc()
693 reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src); in CLOCK_SetIpSrc()
699 (*(volatile uint32_t *)(uint32_t)name) = reg & ~PCC_CLKCFG_CGC_MASK; in CLOCK_SetIpSrc()
700 (*(volatile uint32_t *)(uint32_t)name) = reg; in CLOCK_SetIpSrc()
719 uint32_t reg = (*(volatile uint32_t *)(uint32_t)name); in CLOCK_SetIpSrcDiv() local
721 assert((reg & PCC_CLKCFG_PR_MASK) != 0UL); in CLOCK_SetIpSrcDiv()
722 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrcDiv()
724 …reg = (reg & ~(PCC_CLKCFG_PCS_MASK | PCC_CLKCFG_FRAC_MASK | PCC_CLKCFG_PCD_MASK)) | PCC_CLKCFG_PCS… in CLOCK_SetIpSrcDiv()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/drivers/ |
| D | fsl_clock.h | 688 uint32_t reg = (*(volatile uint32_t *)(uint32_t)name); in CLOCK_SetIpSrc() local
690 assert((reg & PCC_CLKCFG_PR_MASK) != 0UL); in CLOCK_SetIpSrc()
691 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrc()
693 reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src); in CLOCK_SetIpSrc()
699 (*(volatile uint32_t *)(uint32_t)name) = reg & ~PCC_CLKCFG_CGC_MASK; in CLOCK_SetIpSrc()
700 (*(volatile uint32_t *)(uint32_t)name) = reg; in CLOCK_SetIpSrc()
719 uint32_t reg = (*(volatile uint32_t *)(uint32_t)name); in CLOCK_SetIpSrcDiv() local
721 assert((reg & PCC_CLKCFG_PR_MASK) != 0UL); in CLOCK_SetIpSrcDiv()
722 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrcDiv()
724 …reg = (reg & ~(PCC_CLKCFG_PCS_MASK | PCC_CLKCFG_FRAC_MASK | PCC_CLKCFG_PCD_MASK)) | PCC_CLKCFG_PCS… in CLOCK_SetIpSrcDiv()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/sysctr/ |
| D | fsl_sysctr.c | 92 uint32_t reg; in SYSCTR_Init() local
98 reg = ctrlBase->CNTCR; in SYSCTR_Init()
100 reg = pConfig->enableDebugHalt ? (reg | SYS_CTR_CONTROL_CNTCR_HDBG_MASK) : in SYSCTR_Init()
101 (reg & ~SYS_CTR_CONTROL_CNTCR_HDBG_MASK); in SYSCTR_Init()
103 ctrlBase->CNTCR = reg; in SYSCTR_Init()
105 reg = ctrlBase->CNTCR2; in SYSCTR_Init()
107 reg = pConfig->enableHardwareFrequencyChange ? (reg | SYS_CTR_CONTROL_CNTCR2_HWFC_EN_MASK) : in SYSCTR_Init()
108 (reg & ~SYS_CTR_CONTROL_CNTCR2_HWFC_EN_MASK); in SYSCTR_Init()
110 ctrlBase->CNTCR2 = reg; in SYSCTR_Init()
154 uint32_t reg; in SYSCTR_SetCounterClockSource() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/vref/ |
| D | fsl_vref.c | 86 uint8_t reg = 0U; in VREF_Init() local
100 reg = base->VREFH_SC; in VREF_Init()
102 reg = base->SC; in VREF_Init()
105 reg &= ~(uint8_t)VREF_SC_MODE_LV_MASK; in VREF_Init()
107 reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U); in VREF_Init()
110 reg |= VREF_SC_ICOMPEN(1U); in VREF_Init()
113 reg |= VREF_SC_VREFEN(1U); in VREF_Init()
116 base->VREFH_SC = reg; in VREF_Init()
118 base->SC = reg; in VREF_Init()
121 reg = base->VREFL_TRM; in VREF_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/ |
| D | fsl_clock.h | 925 uint32_t reg = (*(volatile uint32_t *)(uint32_t)name); in CLOCK_SetIpSrc() local
927 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_SetIpSrc()
928 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrc()
930 reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src); in CLOCK_SetIpSrc()
936 (*(volatile uint32_t *)(uint32_t)name) = reg & ~PCC_CLKCFG_CGC_MASK; in CLOCK_SetIpSrc()
937 (*(volatile uint32_t *)(uint32_t)name) = reg; in CLOCK_SetIpSrc()
956 uint32_t reg = (*(volatile uint32_t *)(uint32_t)name); in CLOCK_SetIpSrcDiv() local
958 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_SetIpSrcDiv()
959 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrcDiv()
963 reg = in CLOCK_SetIpSrcDiv()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/ |
| D | fsl_clock.h | 925 uint32_t reg = (*(volatile uint32_t *)(uint32_t)name); in CLOCK_SetIpSrc() local
927 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_SetIpSrc()
928 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrc()
930 reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src); in CLOCK_SetIpSrc()
936 (*(volatile uint32_t *)(uint32_t)name) = reg & ~PCC_CLKCFG_CGC_MASK; in CLOCK_SetIpSrc()
937 (*(volatile uint32_t *)(uint32_t)name) = reg; in CLOCK_SetIpSrc()
956 uint32_t reg = (*(volatile uint32_t *)(uint32_t)name); in CLOCK_SetIpSrcDiv() local
958 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_SetIpSrcDiv()
959 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrcDiv()
963 reg = in CLOCK_SetIpSrcDiv()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_cmc/ |
| D | fsl_cmc.c | 42 uint32_t reg; in CMC_SetClockMode() local
44 reg = base->CKCTRL; in CMC_SetClockMode()
45 reg &= ~CMC_CKCTRL_CKMODE_MASK; in CMC_SetClockMode()
46 reg |= CMC_CKCTRL_CKMODE((mode)); in CMC_SetClockMode()
47 base->CKCTRL = reg; in CMC_SetClockMode()
66 uint32_t reg; in CMC_SetPowerModeProtection() local
68 reg = base->PMPROT; in CMC_SetPowerModeProtection()
69 reg &= ~0xFUL; in CMC_SetPowerModeProtection()
70 reg |= allowedModes; in CMC_SetPowerModeProtection()
72 base->PMPROT = reg; in CMC_SetPowerModeProtection()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_spc/ |
| D | fsl_spc.c | 68 uint32_t reg; in SPC_GetPeriphIOIsolationStatus() local
70 reg = base->SC; in SPC_GetPeriphIOIsolationStatus()
71 return (uint8_t)((reg & SPC_SC_ISO_CLR_MASK) >> SPC_SC_ISO_CLR_SHIFT); in SPC_GetPeriphIOIsolationStatus()
86 uint32_t reg; in SPC_SetLowPowerRequestConfig() local
88 reg = base->LPREQ_CFG; in SPC_SetLowPowerRequestConfig()
89 reg &= ~(SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL_MASK | SPC_LPREQ_CFG_LPREQOV_MASK); in SPC_SetLowPowerRequestConfig()
93 reg |= SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL((uint8_t)(config->polarity)) | in SPC_SetLowPowerRequestConfig()
98 reg &= ~SPC_LPREQ_CFG_LPREQOE_MASK; in SPC_SetLowPowerRequestConfig()
101 base->LPREQ_CFG = reg; in SPC_SetLowPowerRequestConfig()
115 uint32_t reg; in SPC_ConfigVddCoreGlitchDetector() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/pwm/ |
| D | fsl_pwm.c | 270 uint16_t reg; in PWM_Init() local
296 reg = base->SM[subModule].CTRL2; in PWM_Init()
301 reg &= in PWM_Init()
307 reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) | in PWM_Init()
318 reg |= PWM_CTRL2_INDEP_MASK; in PWM_Init()
330 base->SM[subModule].CTRL2 = reg; in PWM_Init()
332 reg = base->SM[subModule].CTRL; in PWM_Init()
335 reg &= ~(uint16_t)(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK); in PWM_Init()
336 reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency)); in PWM_Init()
342 reg |= PWM_CTRL_LDMOD_MASK; in PWM_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/ |
| D | fsl_clock.h | 689 uint32_t reg = (*(volatile uint32_t *)((uint32_t)name)); in CLOCK_SetIpSrc() local
691 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_SetIpSrc()
692 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrc()
694 reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src); in CLOCK_SetIpSrc()
700 (*(volatile uint32_t *)((uint32_t)name)) = reg & ~PCC_CLKCFG_CGC_MASK; in CLOCK_SetIpSrc()
701 (*(volatile uint32_t *)((uint32_t)name)) = reg; in CLOCK_SetIpSrc()
916 uint32_t reg = SCG->SOSCDIV; in CLOCK_SetSysOscAsyncClkDiv() local
921 reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider); in CLOCK_SetSysOscAsyncClkDiv()
924 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
928 SCG->SOSCDIV = reg; in CLOCK_SetSysOscAsyncClkDiv()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/drivers/ |
| D | fsl_clock.h | 689 uint32_t reg = (*(volatile uint32_t *)((uint32_t)name)); in CLOCK_SetIpSrc() local
691 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_SetIpSrc()
692 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrc()
694 reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src); in CLOCK_SetIpSrc()
700 (*(volatile uint32_t *)((uint32_t)name)) = reg & ~PCC_CLKCFG_CGC_MASK; in CLOCK_SetIpSrc()
701 (*(volatile uint32_t *)((uint32_t)name)) = reg; in CLOCK_SetIpSrc()
916 uint32_t reg = SCG->SOSCDIV; in CLOCK_SetSysOscAsyncClkDiv() local
921 reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider); in CLOCK_SetSysOscAsyncClkDiv()
924 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
928 SCG->SOSCDIV = reg; in CLOCK_SetSysOscAsyncClkDiv()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/ |
| D | fsl_clock.h | 683 uint32_t reg = (*(volatile uint32_t *)((uint32_t)name)); in CLOCK_SetIpSrc() local
685 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_SetIpSrc()
686 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot… in CLOCK_SetIpSrc()
688 reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src); in CLOCK_SetIpSrc()
694 (*(volatile uint32_t *)((uint32_t)name)) = reg & ~PCC_CLKCFG_CGC_MASK; in CLOCK_SetIpSrc()
695 (*(volatile uint32_t *)((uint32_t)name)) = reg; in CLOCK_SetIpSrc()
910 uint32_t reg = SCG->SOSCDIV; in CLOCK_SetSysOscAsyncClkDiv() local
915 reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider); in CLOCK_SetSysOscAsyncClkDiv()
918 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
922 SCG->SOSCDIV = reg; in CLOCK_SetSysOscAsyncClkDiv()
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