688     uint32_t reg = (*(volatile uint32_t *)(uint32_t)name);  in CLOCK_SetIpSrc()  local
690     assert((reg & PCC_CLKCFG_PR_MASK) != 0UL);  in CLOCK_SetIpSrc()
691 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot…  in CLOCK_SetIpSrc()
693     reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src);  in CLOCK_SetIpSrc()
699     (*(volatile uint32_t *)(uint32_t)name) = reg & ~PCC_CLKCFG_CGC_MASK;  in CLOCK_SetIpSrc()
700     (*(volatile uint32_t *)(uint32_t)name) = reg;  in CLOCK_SetIpSrc()
719     uint32_t reg = (*(volatile uint32_t *)(uint32_t)name);  in CLOCK_SetIpSrcDiv()  local
721     assert((reg & PCC_CLKCFG_PR_MASK) != 0UL);  in CLOCK_SetIpSrcDiv()
722 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot…  in CLOCK_SetIpSrcDiv()
724 …reg = (reg & ~(PCC_CLKCFG_PCS_MASK | PCC_CLKCFG_FRAC_MASK | PCC_CLKCFG_PCD_MASK)) | PCC_CLKCFG_PCS…  in CLOCK_SetIpSrcDiv()
731     (*(volatile uint32_t *)(uint32_t)name) = reg & ~PCC_CLKCFG_CGC_MASK;  in CLOCK_SetIpSrcDiv()
732     (*(volatile uint32_t *)(uint32_t)name) = reg;  in CLOCK_SetIpSrcDiv()
972     uint32_t reg = SCG->SOSCDIV;  in CLOCK_SetSysOscAsyncClkDiv()  local
977             reg = (reg & ~SCG_SOSCDIV_SOSCDIV3_MASK) | SCG_SOSCDIV_SOSCDIV3(divider);  in CLOCK_SetSysOscAsyncClkDiv()
980             reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider);  in CLOCK_SetSysOscAsyncClkDiv()
983             reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider);  in CLOCK_SetSysOscAsyncClkDiv()
987     SCG->SOSCDIV = reg;  in CLOCK_SetSysOscAsyncClkDiv()
1033     uint32_t reg = SCG->SOSCCSR;  in CLOCK_SetSysOscMonitorMode()  local
1035     reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);  in CLOCK_SetSysOscMonitorMode()
1037     reg |= (uint32_t)mode;  in CLOCK_SetSysOscMonitorMode()
1039     SCG->SOSCCSR = reg;  in CLOCK_SetSysOscMonitorMode()
1098     uint32_t reg = SCG->SIRCDIV;  in CLOCK_SetSircAsyncClkDiv()  local
1103             reg = (reg & ~SCG_SIRCDIV_SIRCDIV3_MASK) | SCG_SIRCDIV_SIRCDIV3(divider);  in CLOCK_SetSircAsyncClkDiv()
1106             reg = (reg & ~SCG_SIRCDIV_SIRCDIV2_MASK) | SCG_SIRCDIV_SIRCDIV2(divider);  in CLOCK_SetSircAsyncClkDiv()
1109             reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider);  in CLOCK_SetSircAsyncClkDiv()
1113     SCG->SIRCDIV = reg;  in CLOCK_SetSircAsyncClkDiv()
1186     uint32_t reg = SCG->FIRCDIV;  in CLOCK_SetFircAsyncClkDiv()  local
1191             reg = (reg & ~SCG_FIRCDIV_FIRCDIV3_MASK) | SCG_FIRCDIV_FIRCDIV3(divider);  in CLOCK_SetFircAsyncClkDiv()
1194             reg = (reg & ~SCG_FIRCDIV_FIRCDIV2_MASK) | SCG_FIRCDIV_FIRCDIV2(divider);  in CLOCK_SetFircAsyncClkDiv()
1197             reg = (reg & ~SCG_FIRCDIV_FIRCDIV1_MASK) | SCG_FIRCDIV_FIRCDIV1(divider);  in CLOCK_SetFircAsyncClkDiv()
1201     SCG->FIRCDIV = reg;  in CLOCK_SetFircAsyncClkDiv()
1326     uint32_t reg = SCG->SPLLDIV;  in CLOCK_SetSysPllAsyncClkDiv()  local
1331             reg = (reg & ~SCG_SPLLDIV_SPLLDIV3_MASK) | SCG_SPLLDIV_SPLLDIV3(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1334             reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1337             reg = (reg & ~SCG_SPLLDIV_SPLLDIV1_MASK) | SCG_SPLLDIV_SPLLDIV1(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1341     SCG->SPLLDIV = reg;  in CLOCK_SetSysPllAsyncClkDiv()
1387     uint32_t reg = SCG->SPLLCSR;  in CLOCK_SetSysPllMonitorMode()  local
1389     reg &= ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK);  in CLOCK_SetSysPllMonitorMode()
1391     reg |= (uint32_t)mode;  in CLOCK_SetSysPllMonitorMode()
1393     SCG->SPLLCSR = reg;  in CLOCK_SetSysPllMonitorMode()