689     uint32_t reg = (*(volatile uint32_t *)((uint32_t)name));  in CLOCK_SetIpSrc()  local
691     assert(reg & PCC_CLKCFG_PR_MASK);  in CLOCK_SetIpSrc()
692 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot…  in CLOCK_SetIpSrc()
694     reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src);  in CLOCK_SetIpSrc()
700     (*(volatile uint32_t *)((uint32_t)name)) = reg & ~PCC_CLKCFG_CGC_MASK;  in CLOCK_SetIpSrc()
701     (*(volatile uint32_t *)((uint32_t)name)) = reg;  in CLOCK_SetIpSrc()
916     uint32_t reg = SCG->SOSCDIV;  in CLOCK_SetSysOscAsyncClkDiv()  local
921             reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider);  in CLOCK_SetSysOscAsyncClkDiv()
924             reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider);  in CLOCK_SetSysOscAsyncClkDiv()
928     SCG->SOSCDIV = reg;  in CLOCK_SetSysOscAsyncClkDiv()
974     uint32_t reg = SCG->SOSCCSR;  in CLOCK_SetSysOscMonitorMode()  local
976     reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);  in CLOCK_SetSysOscMonitorMode()
978     reg |= (uint32_t)mode;  in CLOCK_SetSysOscMonitorMode()
980     SCG->SOSCCSR = reg;  in CLOCK_SetSysOscMonitorMode()
1039     uint32_t reg = SCG->SIRCDIV;  in CLOCK_SetSircAsyncClkDiv()  local
1044             reg = (reg & ~SCG_SIRCDIV_SIRCDIV2_MASK) | SCG_SIRCDIV_SIRCDIV2(divider);  in CLOCK_SetSircAsyncClkDiv()
1047             reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider);  in CLOCK_SetSircAsyncClkDiv()
1051     SCG->SIRCDIV = reg;  in CLOCK_SetSircAsyncClkDiv()
1124     uint32_t reg = SCG->FIRCDIV;  in CLOCK_SetFircAsyncClkDiv()  local
1129             reg = (reg & ~SCG_FIRCDIV_FIRCDIV2_MASK) | SCG_FIRCDIV_FIRCDIV2(divider);  in CLOCK_SetFircAsyncClkDiv()
1132             reg = (reg & ~SCG_FIRCDIV_FIRCDIV1_MASK) | SCG_FIRCDIV_FIRCDIV1(divider);  in CLOCK_SetFircAsyncClkDiv()
1136     SCG->FIRCDIV = reg;  in CLOCK_SetFircAsyncClkDiv()
1265     uint32_t reg = SCG->SPLLDIV;  in CLOCK_SetSysPllAsyncClkDiv()  local
1270             reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1273             reg = (reg & ~SCG_SPLLDIV_SPLLDIV1_MASK) | SCG_SPLLDIV_SPLLDIV1(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1277     SCG->SPLLDIV = reg;  in CLOCK_SetSysPllAsyncClkDiv()
1323     uint32_t reg = SCG->SPLLCSR;  in CLOCK_SetSysPllMonitorMode()  local
1325     reg &= ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK);  in CLOCK_SetSysPllMonitorMode()
1327     reg |= (uint32_t)mode;  in CLOCK_SetSysPllMonitorMode()
1329     SCG->SPLLCSR = reg;  in CLOCK_SetSysPllMonitorMode()