925     uint32_t reg = (*(volatile uint32_t *)(uint32_t)name);  in CLOCK_SetIpSrc()  local
927     assert(reg & PCC_CLKCFG_PR_MASK);  in CLOCK_SetIpSrc()
928 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot…  in CLOCK_SetIpSrc()
930     reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src);  in CLOCK_SetIpSrc()
936     (*(volatile uint32_t *)(uint32_t)name) = reg & ~PCC_CLKCFG_CGC_MASK;  in CLOCK_SetIpSrc()
937     (*(volatile uint32_t *)(uint32_t)name) = reg;  in CLOCK_SetIpSrc()
956     uint32_t reg = (*(volatile uint32_t *)(uint32_t)name);  in CLOCK_SetIpSrcDiv()  local
958     assert(reg & PCC_CLKCFG_PR_MASK);  in CLOCK_SetIpSrcDiv()
959 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot…  in CLOCK_SetIpSrcDiv()
963         reg =  in CLOCK_SetIpSrcDiv()
964 …(reg & ~(PCC_CLKCFG_PCS_MASK | PCC1_PCC_SAI1_PCD_MASK)) | PCC_CLKCFG_PCS(src) | PCC1_PCC_SAI1_PCD(…  in CLOCK_SetIpSrcDiv()
968 …reg = (reg & ~(PCC_CLKCFG_PCS_MASK | PCC_CLKCFG_FRAC_MASK | PCC_CLKCFG_PCD_MASK)) | PCC_CLKCFG_PCS…  in CLOCK_SetIpSrcDiv()
976     (*(volatile uint32_t *)(uint32_t)name) = reg & ~PCC_CLKCFG_CGC_MASK;  in CLOCK_SetIpSrcDiv()
977     (*(volatile uint32_t *)(uint32_t)name) = reg;  in CLOCK_SetIpSrcDiv()
1189     uint32_t reg = SCG->SOSCDIV;  in CLOCK_SetSysOscAsyncClkDiv()  local
1194             reg = (reg & ~SCG_SOSCDIV_SOSCDIV3_MASK) | SCG_SOSCDIV_SOSCDIV3(divider);  in CLOCK_SetSysOscAsyncClkDiv()
1197             reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider);  in CLOCK_SetSysOscAsyncClkDiv()
1200             reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider);  in CLOCK_SetSysOscAsyncClkDiv()
1204     SCG->SOSCDIV = reg;  in CLOCK_SetSysOscAsyncClkDiv()
1250     uint32_t reg = SCG->SOSCCSR;  in CLOCK_SetSysOscMonitorMode()  local
1252     reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);  in CLOCK_SetSysOscMonitorMode()
1254     reg |= (uint32_t)mode;  in CLOCK_SetSysOscMonitorMode()
1256     SCG->SOSCCSR = reg;  in CLOCK_SetSysOscMonitorMode()
1315     uint32_t reg = SCG->SIRCDIV;  in CLOCK_SetSircAsyncClkDiv()  local
1320             reg = (reg & ~SCG_SIRCDIV_SIRCDIV3_MASK) | SCG_SIRCDIV_SIRCDIV3(divider);  in CLOCK_SetSircAsyncClkDiv()
1323             reg = (reg & ~SCG_SIRCDIV_SIRCDIV2_MASK) | SCG_SIRCDIV_SIRCDIV2(divider);  in CLOCK_SetSircAsyncClkDiv()
1326             reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider);  in CLOCK_SetSircAsyncClkDiv()
1330     SCG->SIRCDIV = reg;  in CLOCK_SetSircAsyncClkDiv()
1424     uint32_t reg = SCG->FIRCDIV;  in CLOCK_SetFircAsyncClkDiv()  local
1429             reg = (reg & ~SCG_FIRCDIV_FIRCDIV3_MASK) | SCG_FIRCDIV_FIRCDIV3(divider);  in CLOCK_SetFircAsyncClkDiv()
1432             reg = (reg & ~SCG_FIRCDIV_FIRCDIV2_MASK) | SCG_FIRCDIV_FIRCDIV2(divider);  in CLOCK_SetFircAsyncClkDiv()
1435             reg = (reg & ~SCG_FIRCDIV_FIRCDIV1_MASK) | SCG_FIRCDIV_FIRCDIV1(divider);  in CLOCK_SetFircAsyncClkDiv()
1439     SCG->FIRCDIV = reg;  in CLOCK_SetFircAsyncClkDiv()
1521     uint32_t reg = SCG->ROSCCSR;  in CLOCK_SetRtcOscMonitorMode()  local
1523     reg &= ~(SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK);  in CLOCK_SetRtcOscMonitorMode()
1525     reg |= (uint32_t)mode;  in CLOCK_SetRtcOscMonitorMode()
1527     SCG->ROSCCSR = reg;  in CLOCK_SetRtcOscMonitorMode()
1602     uint32_t reg = SCG->APLLDIV;  in CLOCK_SetAuxPllAsyncClkDiv()  local
1607             reg = (reg & ~SCG_APLLDIV_APLLDIV1_MASK) | SCG_APLLDIV_APLLDIV1(divider);  in CLOCK_SetAuxPllAsyncClkDiv()
1610             reg = (reg & ~SCG_APLLDIV_APLLDIV2_MASK) | SCG_APLLDIV_APLLDIV2(divider);  in CLOCK_SetAuxPllAsyncClkDiv()
1613             reg = (reg & ~SCG_APLLDIV_APLLDIV1_MASK) | SCG_APLLDIV_APLLDIV1(divider);  in CLOCK_SetAuxPllAsyncClkDiv()
1617     SCG->APLLDIV = reg;  in CLOCK_SetAuxPllAsyncClkDiv()
1787     uint32_t reg = SCG->SPLLDIV;  in CLOCK_SetSysPllAsyncClkDiv()  local
1792             reg = (reg & ~SCG_SPLLDIV_SPLLDIV3_MASK) | SCG_SPLLDIV_SPLLDIV3(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1795             reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1798             reg = (reg & ~SCG_SPLLDIV_SPLLDIV1_MASK) | SCG_SPLLDIV_SPLLDIV1(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1802     SCG->SPLLDIV = reg;  in CLOCK_SetSysPllAsyncClkDiv()