96     uint32_t reg = 0, syncReg = 0;  in FTM_SetPwmSync()  local
105     reg = base->COMBINE;  in FTM_SetPwmSync()
109         reg |= (1UL << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber)));  in FTM_SetPwmSync()
111     base->COMBINE = reg;  in FTM_SetPwmSync()
113     reg = base->SYNCONF;  in FTM_SetPwmSync()
116 …reg |= (FTM_SYNCONF_SYNCMODE_MASK | FTM_SYNCONF_CNTINC_MASK | FTM_SYNCONF_INVC_MASK | FTM_SYNCONF_…  in FTM_SetPwmSync()
121 …reg |= (FTM_SYNCONF_SWWRBUF_MASK | FTM_SYNCONF_SWINVC_MASK | FTM_SYNCONF_SWSOC_MASK | FTM_SYNCONF_…  in FTM_SetPwmSync()
125             reg |= FTM_SYNCONF_SWRSTCNT_MASK;  in FTM_SetPwmSync()
132 …reg |= (FTM_SYNCONF_HWWRBUF_MASK | FTM_SYNCONF_HWINVC_MASK | FTM_SYNCONF_HWSOC_MASK | FTM_SYNCONF_…  in FTM_SetPwmSync()
136             reg |= FTM_SYNCONF_HWRSTCNT_MASK;  in FTM_SetPwmSync()
158     base->SYNCONF = reg;  in FTM_SetPwmSync()
164     uint32_t reg        = 0;  in FTM_SetReloadPoints()  local
173     reg = base->COMBINE;  in FTM_SetReloadPoints()
177         reg |= (1UL << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber)));  in FTM_SetReloadPoints()
179     base->COMBINE = reg;  in FTM_SetReloadPoints()
182     reg = base->PWMLOAD;  in FTM_SetReloadPoints()
185     reg &= ~((1UL << (uint32_t)chnlCount) - 1U);  in FTM_SetReloadPoints()
186     reg |= (reloadPoints & ((1UL << (uint32_t)chnlCount) - 1U));  in FTM_SetReloadPoints()
192         reg |= FTM_PWMLOAD_HCSEL_MASK;  in FTM_SetReloadPoints()
196         reg &= ~FTM_PWMLOAD_HCSEL_MASK;  in FTM_SetReloadPoints()
200     base->PWMLOAD = reg;  in FTM_SetReloadPoints()
203     reg = base->SYNC;  in FTM_SetReloadPoints()
207         reg |= FTM_SYNC_CNTMAX_MASK;  in FTM_SetReloadPoints()
211         reg &= ~FTM_SYNC_CNTMAX_MASK;  in FTM_SetReloadPoints()
217         reg |= FTM_SYNC_CNTMIN_MASK;  in FTM_SetReloadPoints()
221         reg &= ~FTM_SYNC_CNTMIN_MASK;  in FTM_SetReloadPoints()
223     base->SYNC = reg;  in FTM_SetReloadPoints()
245     uint32_t reg;  in FTM_Init()  local
322         reg = base->FLTCTRL;  in FTM_Init()
323         reg &= ~FTM_FLTCTRL_FFVAL_MASK;  in FTM_Init()
324         reg |= FTM_FLTCTRL_FFVAL(config->faultFilterValue);  in FTM_Init()
325         base->FLTCTRL = reg;  in FTM_Init()
329     reg = base->FLTCTRL;  in FTM_Init()
330     reg &= ~FTM_FLTCTRL_FFVAL_MASK;  in FTM_Init()
331     reg |= FTM_FLTCTRL_FFVAL(config->faultFilterValue);  in FTM_Init()
332     base->FLTCTRL = reg;  in FTM_Init()
438     uint32_t mod, reg;  in FTM_SetupPwm()  local
497             reg = base->CONTROLS[chnlParams->chnlNumber].CnSC;  in FTM_SetupPwm()
498 …         reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupPwm()
501             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwm()
504             reg |= FTM_CnSC_MSB(1U);  in FTM_SetupPwm()
507             base->CONTROLS[chnlParams->chnlNumber].CnSC = reg;  in FTM_SetupPwm()
543             reg = base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC;  in FTM_SetupPwm()
544 …         reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupPwm()
547             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwm()
550             base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC = reg;  in FTM_SetupPwm()
553             reg = base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC;  in FTM_SetupPwm()
554 …         reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupPwm()
557             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwm()
560             base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC = reg;  in FTM_SetupPwm()
671     uint32_t reg = base->CONTROLS[chnlNumber].CnSC;  in FTM_UpdateChnlEdgeLevelSelect()  local
674     reg &= ~(FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_UpdateChnlEdgeLevelSelect()
675     reg |= ((uint32_t)level << FTM_CnSC_ELSA_SHIFT) & (FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_UpdateChnlEdgeLevelSelect()
677     base->CONTROLS[chnlNumber].CnSC = reg;  in FTM_UpdateChnlEdgeLevelSelect()
706     uint32_t reg;  in FTM_SetupPwmMode()  local
734             reg = base->CONTROLS[chnlParams->chnlNumber].CnSC;  in FTM_SetupPwmMode()
735 …         reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupPwmMode()
738             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwmMode()
741             reg |= FTM_CnSC_MSB(1U);  in FTM_SetupPwmMode()
744             base->CONTROLS[chnlParams->chnlNumber].CnSC = reg;  in FTM_SetupPwmMode()
786             reg = base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC;  in FTM_SetupPwmMode()
787 …         reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupPwmMode()
790             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwmMode()
793             base->CONTROLS[((uint32_t)chnlParams->chnlNumber) * 2U].CnSC = reg;  in FTM_SetupPwmMode()
796             reg = base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC;  in FTM_SetupPwmMode()
797 …         reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupPwmMode()
800             reg |= (uint32_t)chnlParams->level << FTM_CnSC_ELSA_SHIFT;  in FTM_SetupPwmMode()
803             base->CONTROLS[(((uint32_t)chnlParams->chnlNumber) * 2U) + 1U].CnSC = reg;  in FTM_SetupPwmMode()
848     uint32_t reg;  in FTM_SetupInputCapture()  local
861     reg = base->CONTROLS[chnlNumber].CnSC;  in FTM_SetupInputCapture()
862     reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupInputCapture()
863     reg |= (uint32_t)captureMode;  in FTM_SetupInputCapture()
866     base->CONTROLS[chnlNumber].CnSC = reg;  in FTM_SetupInputCapture()
870         reg = base->FILTER;  in FTM_SetupInputCapture()
871 …  reg &= ~((uint32_t)FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * (uint32_t)chnlNumber));  in FTM_SetupInputCapture()
872         reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * (uint32_t)chnlNumber));  in FTM_SetupInputCapture()
873         base->FILTER = reg;  in FTM_SetupInputCapture()
897     uint32_t reg;  in FTM_SetupOutputCompare()  local
910     reg = base->CONTROLS[chnlNumber].CnSC;  in FTM_SetupOutputCompare()
911     reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupOutputCompare()
912     reg |= (uint32_t)compareMode;  in FTM_SetupOutputCompare()
914     base->CONTROLS[chnlNumber].CnSC = reg;  in FTM_SetupOutputCompare()
946     uint32_t reg;  in FTM_SetupDualEdgeCapture()  local
948     reg = base->COMBINE;  in FTM_SetupDualEdgeCapture()
950 …reg &= ~(1UL << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlPairNumb…  in FTM_SetupDualEdgeCapture()
952 …reg |= (1UL << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlPairNumbe…  in FTM_SetupDualEdgeCapture()
953 …reg |= (1UL << (FTM_COMBINE_DECAP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (uint32_t)chnlPairNumber)…  in FTM_SetupDualEdgeCapture()
954     base->COMBINE = reg;  in FTM_SetupDualEdgeCapture()
957     reg = base->CONTROLS[((uint32_t)chnlPairNumber) * 2U].CnSC;  in FTM_SetupDualEdgeCapture()
958     reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupDualEdgeCapture()
959     reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->currChanEdgeMode);  in FTM_SetupDualEdgeCapture()
960     base->CONTROLS[((uint32_t)chnlPairNumber) * 2U].CnSC = reg;  in FTM_SetupDualEdgeCapture()
962     reg = base->CONTROLS[(((uint32_t)chnlPairNumber) * 2U) + 1U].CnSC;  in FTM_SetupDualEdgeCapture()
963     reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);  in FTM_SetupDualEdgeCapture()
964     reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->nextChanEdgeMode);  in FTM_SetupDualEdgeCapture()
965     base->CONTROLS[(((uint32_t)chnlPairNumber) * 2U) + 1U].CnSC = reg;  in FTM_SetupDualEdgeCapture()
970         reg = base->FILTER;  in FTM_SetupDualEdgeCapture()
971 …reg &= ~((uint32_t)FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * (uint32_t)chnlPairNumber…  in FTM_SetupDualEdgeCapture()
972         reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * (uint32_t)chnlPairNumber));  in FTM_SetupDualEdgeCapture()
973         base->FILTER = reg;  in FTM_SetupDualEdgeCapture()
998     uint32_t reg;  in FTM_SetupQuadDecode()  local
1003         reg = base->FILTER;  in FTM_SetupQuadDecode()
1004         reg &= ~(FTM_FILTER_CH0FVAL_MASK);  in FTM_SetupQuadDecode()
1005         reg |= FTM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal);  in FTM_SetupQuadDecode()
1006         base->FILTER = reg;  in FTM_SetupQuadDecode()
1012         reg = base->FILTER;  in FTM_SetupQuadDecode()
1013         reg &= ~(FTM_FILTER_CH1FVAL_MASK);  in FTM_SetupQuadDecode()
1014         reg |= FTM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal);  in FTM_SetupQuadDecode()
1015         base->FILTER = reg;  in FTM_SetupQuadDecode()
1019     reg = base->QDCTRL;  in FTM_SetupQuadDecode()
1020 …reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QD…  in FTM_SetupQuadDecode()
1022     reg |= (FTM_QDCTRL_QUADMODE(quadMode) | FTM_QDCTRL_PHAFLTREN(phaseAParams->enablePhaseFilter) |  in FTM_SetupQuadDecode()
1025     base->QDCTRL = reg;  in FTM_SetupQuadDecode()