683     uint32_t reg = (*(volatile uint32_t *)((uint32_t)name));  in CLOCK_SetIpSrc()  local
685     assert(reg & PCC_CLKCFG_PR_MASK);  in CLOCK_SetIpSrc()
686 …assert(0UL == (reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by ot…  in CLOCK_SetIpSrc()
688     reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src);  in CLOCK_SetIpSrc()
694     (*(volatile uint32_t *)((uint32_t)name)) = reg & ~PCC_CLKCFG_CGC_MASK;  in CLOCK_SetIpSrc()
695     (*(volatile uint32_t *)((uint32_t)name)) = reg;  in CLOCK_SetIpSrc()
910     uint32_t reg = SCG->SOSCDIV;  in CLOCK_SetSysOscAsyncClkDiv()  local
915             reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider);  in CLOCK_SetSysOscAsyncClkDiv()
918             reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider);  in CLOCK_SetSysOscAsyncClkDiv()
922     SCG->SOSCDIV = reg;  in CLOCK_SetSysOscAsyncClkDiv()
968     uint32_t reg = SCG->SOSCCSR;  in CLOCK_SetSysOscMonitorMode()  local
970     reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);  in CLOCK_SetSysOscMonitorMode()
972     reg |= (uint32_t)mode;  in CLOCK_SetSysOscMonitorMode()
974     SCG->SOSCCSR = reg;  in CLOCK_SetSysOscMonitorMode()
1033     uint32_t reg = SCG->SIRCDIV;  in CLOCK_SetSircAsyncClkDiv()  local
1038             reg = (reg & ~SCG_SIRCDIV_SIRCDIV2_MASK) | SCG_SIRCDIV_SIRCDIV2(divider);  in CLOCK_SetSircAsyncClkDiv()
1041             reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider);  in CLOCK_SetSircAsyncClkDiv()
1045     SCG->SIRCDIV = reg;  in CLOCK_SetSircAsyncClkDiv()
1118     uint32_t reg = SCG->FIRCDIV;  in CLOCK_SetFircAsyncClkDiv()  local
1123             reg = (reg & ~SCG_FIRCDIV_FIRCDIV2_MASK) | SCG_FIRCDIV_FIRCDIV2(divider);  in CLOCK_SetFircAsyncClkDiv()
1126             reg = (reg & ~SCG_FIRCDIV_FIRCDIV1_MASK) | SCG_FIRCDIV_FIRCDIV1(divider);  in CLOCK_SetFircAsyncClkDiv()
1130     SCG->FIRCDIV = reg;  in CLOCK_SetFircAsyncClkDiv()
1259     uint32_t reg = SCG->SPLLDIV;  in CLOCK_SetSysPllAsyncClkDiv()  local
1264             reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1267             reg = (reg & ~SCG_SPLLDIV_SPLLDIV1_MASK) | SCG_SPLLDIV_SPLLDIV1(divider);  in CLOCK_SetSysPllAsyncClkDiv()
1271     SCG->SPLLDIV = reg;  in CLOCK_SetSysPllAsyncClkDiv()
1317     uint32_t reg = SCG->SPLLCSR;  in CLOCK_SetSysPllMonitorMode()  local
1319     reg &= ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK);  in CLOCK_SetSysPllMonitorMode()
1321     reg |= (uint32_t)mode;  in CLOCK_SetSysPllMonitorMode()
1323     SCG->SPLLCSR = reg;  in CLOCK_SetSysPllMonitorMode()