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/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrke18f/
Dclock_config.c73 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
170 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
176 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
182 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
190 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
282 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
288 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
294 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
302 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
402 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrke18f/project_template/
Dclock_config.c74 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
177 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
183 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
189 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
197 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
288 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
294 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
300 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
308 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
417 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmke15z/
Dclock_config.c74 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
169 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
175 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
181 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
188 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
274 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
280 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
286 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
293 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmke15z/project_template/
Dclock_config.c73 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
173 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
178 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
183 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
189 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
285 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
290 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
295 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
301 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmke16z/
Dclock_config.c73 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
170 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
176 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
182 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
189 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
278 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
284 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
290 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
297 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmke16z/project_template/
Dclock_config.c73 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
166 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
171 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
176 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
182 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
268 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
273 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
278 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
284 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmke17z/
Dclock_config.c71 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
165 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
170 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
175 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
181 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
266 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
271 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
276 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
282 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmke17z/project_template/
Dclock_config.c71 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
165 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
170 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
175 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
181 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
266 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
271 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
276 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
282 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-ke15z/
Dclock_config.c68 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
152 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
158 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
164 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
171 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
256 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
262 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
268 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
275 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l3a6/project_template/
Dclock_config.c75 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
152 ….div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock outp…
159 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
167 … .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
251 ….div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock outp…
258 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
266 … .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
355 ….div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by…
362 .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
370 … .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l3a6/
Dclock_config.c75 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
150 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
158 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
167 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
250 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
258 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
267 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
358 .div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
366 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
375 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z4/project_template/
Dclock_config.c72 .enableMode = kSCG_SircEnable, .div2 = kSCG_AsyncClkDivBy2, .range = kSCG_SircRangeHigh}; in CLOCK_CONFIG_FircSafeConfig()
139 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
144 ….div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock outp…
149 .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
155 … .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE12Z7/project_template/
Dclock_config.c72 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
141 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
147 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
153 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
160 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE13Z7/project_template/
Dclock_config.c72 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
141 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
147 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
153 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
160 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z4/project_template/
Dclock_config.c72 .enableMode = kSCG_SircEnable, .div2 = kSCG_AsyncClkDivBy2, .range = kSCG_SircRangeHigh}; in CLOCK_CONFIG_FircSafeConfig()
139 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
144 ….div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock outp…
149 .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
155 … .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14Z7/project_template/
Dclock_config.c72 .enableMode = kSCG_SircEnable, .div2 = kSCG_AsyncClkDivBy2, .range = kSCG_SircRangeHigh}; in CLOCK_CONFIG_FircSafeConfig()
141 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
147 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
153 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
160 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE17Z7/project_template/
Dclock_config.c72 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
141 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
147 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
153 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
160 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16Z4/project_template/
Dclock_config.c72 .enableMode = kSCG_SircEnable, .div2 = kSCG_AsyncClkDivBy2, .range = kSCG_SircRangeHigh}; in CLOCK_CONFIG_FircSafeConfig()
139 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
144 ….div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock outp…
149 .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
155 … .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE15Z7/project_template/
Dclock_config.c72 .enableMode = kSCG_SircEnable, .div2 = kSCG_AsyncClkDivBy2, .range = kSCG_SircRangeHigh}; in CLOCK_CONFIG_FircSafeConfig()
141 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
147 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
153 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
160 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/project_template/
Dclock_config.c73 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
146 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
153 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
160 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
169 ….div2 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 2: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/project_template/
Dclock_config.c73 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
146 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
153 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
160 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
169 ….div2 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 2: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/project_template/
Dclock_config.c73 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
146 ….div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled …
153 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
160 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
169 ….div2 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 2: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-k32w042/
Dclock_config.c67 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
138 .div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
144 ….div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock outp…
151 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
159 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/project_template/
Dclock_config.c72 .div2 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig()
135 … .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
143 … .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
152 ….div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmcimx7ulp/project_template/
Dclock_config.c36 .div2 = kSCG_AsyncClkDisable,
49 .div2 = kSCG_AsyncClkDisable,
62 .div2 = kSCG_AsyncClkDisable,
77 .div2 = kSCG_AsyncClkDivBy2,
94 .div2 = kSCG_AsyncClkDivBy1,

123