1 /*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v4.1
34 processor: MKE16Z64xxx4
35 package_id: MKE16Z64VLF4
36 mcu_data: ksdk2_0
37 processor_version: 0.0.0
38 board: FRDM-KE16Z
39 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
40 /* clang-format on */
41
42 #include "fsl_smc.h"
43 #include "clock_config.h"
44
45 /*******************************************************************************
46 * Definitions
47 ******************************************************************************/
48
49 /*******************************************************************************
50 * Variables
51 ******************************************************************************/
52 /* System clock frequency. */
53 extern uint32_t SystemCoreClock;
54
55 /*******************************************************************************
56 * Code
57 ******************************************************************************/
58 /*FUNCTION**********************************************************************
59 *
60 * Function Name : CLOCK_CONFIG_FircSafeConfig
61 * Description : This function is used to safely configure FIRC clock.
62 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
63 * Before setting FIRC, change to use SIRC as system clock,
64 * then configure FIRC. After FIRC is set, change back to use FIRC
65 * in case SIRC need to be configured.
66 * Param fircConfig : FIRC configuration.
67 *
68 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)69 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
70 {
71 scg_sys_clk_config_t curConfig;
72 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
73 .div2 = kSCG_AsyncClkDivBy2,
74 .range = kSCG_SircRangeHigh};
75 scg_sys_clk_config_t sysClkSafeConfigSource = {
76 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
77 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
78 .src = kSCG_SysClkSrcSirc /* System clock source */
79 };
80 /* Init Sirc. */
81 CLOCK_InitSirc(&scgSircConfig);
82 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
83 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
84 /* Wait for clock source switch finished. */
85 do
86 {
87 CLOCK_GetCurSysClkConfig(&curConfig);
88 } while (curConfig.src != sysClkSafeConfigSource.src);
89
90 /* Init Firc. */
91 CLOCK_InitFirc(fircConfig);
92 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
93 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
94 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
95 /* Wait for clock source switch finished. */
96 do
97 {
98 CLOCK_GetCurSysClkConfig(&curConfig);
99 } while (curConfig.src != sysClkSafeConfigSource.src);
100 }
101
102 /*******************************************************************************
103 ************************ BOARD_InitBootClocks function ************************
104 ******************************************************************************/
BOARD_InitBootClocks(void)105 void BOARD_InitBootClocks(void)
106 {
107 BOARD_BootClockRUN();
108 }
109
110 /*******************************************************************************
111 ********************** Configuration BOARD_BootClockRUN ***********************
112 ******************************************************************************/
113 /* clang-format off */
114 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
115 !!Configuration
116 name: BOARD_BootClockRUN
117 called_from_default_init: true
118 outputs:
119 - {id: Bus_clock.outFreq, value: 24 MHz}
120 - {id: Core_clock.outFreq, value: 48 MHz}
121 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
122 - {id: FLLDIV2_CLK.outFreq, value: 24 MHz}
123 - {id: Flash_clock.outFreq, value: 24 MHz}
124 - {id: LPO1KCLK.outFreq, value: 1 kHz}
125 - {id: LPO_clock.outFreq, value: 128 kHz}
126 - {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
127 - {id: SIRC_CLK.outFreq, value: 8 MHz}
128 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
129 - {id: SOSC_CLK.outFreq, value: 8 MHz}
130 - {id: System_clock.outFreq, value: 48 MHz}
131 settings:
132 - {id: SCGMode, value: LPFLL}
133 - {id: PCC.PCC_ADC0_SEL.sel, value: SCG.SOSCDIV2_CLK}
134 - {id: PCC.PCC_LPI2C0_SEL.sel, value: SCG.SOSCDIV2_CLK}
135 - {id: PCC.PCC_LPUART0_SEL.sel, value: SCG.SOSCDIV2_CLK}
136 - {id: SCG.FIRCDIV2.scale, value: '1'}
137 - {id: SCG.LPFLLDIV2.scale, value: '2'}
138 - {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
139 - {id: SCG.SIRCDIV2.scale, value: '2'}
140 - {id: SCG.SOSCDIV2.scale, value: '1'}
141 - {id: SCG.TRIMDIV.scale, value: '4'}
142 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
143 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
144 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
145 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
146 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
147 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
148 sources:
149 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
150 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
151 /* clang-format on */
152
153 /*******************************************************************************
154 * Variables for BOARD_BootClockRUN configuration
155 ******************************************************************************/
156 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = {
157 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
158 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
159 .src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
160 };
161 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = {
162 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
163 .enableMode = kSCG_SysOscEnable |
164 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
165 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
166 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
167 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
168 };
169 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = {
170 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
171 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
172 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
173 };
174 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = {
175 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
176 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
177 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
178 .trimConfig = NULL, /* Fast IRC Trim disabled */
179 };
180 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN = {
181 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
182 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
183 .range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
184 .trimConfig = NULL,
185 };
186 /*******************************************************************************
187 * Code for BOARD_BootClockRUN configuration
188 ******************************************************************************/
BOARD_BootClockRUN(void)189 void BOARD_BootClockRUN(void)
190 {
191 scg_sys_clk_config_t curConfig;
192
193 /* Init SOSC according to board configuration. */
194 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
195 /* Set the XTAL0 frequency based on board settings. */
196 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
197 /* Init FIRC. */
198 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
199 /* Init SIRC. */
200 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
201 /* Init LPFLL. */
202 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
203 /* Set SCG to LPFLL mode. */
204 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
205 /* Wait for clock source switch finished. */
206 do
207 {
208 CLOCK_GetCurSysClkConfig(&curConfig);
209 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
210 /* Set SystemCoreClock variable. */
211 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
212 }
213
214 /*******************************************************************************
215 ********************* Configuration BOARD_BootClockVLPR ***********************
216 ******************************************************************************/
217 /* clang-format off */
218 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
219 !!Configuration
220 name: BOARD_BootClockVLPR
221 outputs:
222 - {id: Bus_clock.outFreq, value: 1 MHz}
223 - {id: Core_clock.outFreq, value: 4 MHz}
224 - {id: Flash_clock.outFreq, value: 1 MHz}
225 - {id: LPO1KCLK.outFreq, value: 1 kHz}
226 - {id: LPO_clock.outFreq, value: 128 kHz}
227 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
228 - {id: SOSC_CLK.outFreq, value: 8 MHz}
229 - {id: System_clock.outFreq, value: 4 MHz}
230 settings:
231 - {id: SCGMode, value: SOSC}
232 - {id: powerMode, value: VLPR}
233 - {id: SCG.DIVCORE.scale, value: '2', locked: true}
234 - {id: SCG.DIVSLOW.scale, value: '4', locked: true}
235 - {id: SCG.FIRCDIV2.scale, value: '1'}
236 - {id: SCG.LPFLLDIV2.scale, value: '2'}
237 - {id: SCG.SCSSEL.sel, value: SCG.SOSC}
238 - {id: SCG.SIRCDIV2.scale, value: '2'}
239 - {id: SCG.SOSCDIV2.scale, value: '1'}
240 - {id: 'SCG::RCCR[DIVCORE].bitField', value: BitFieldValue}
241 - {id: 'SCG::RCCR[DIVSLOW].bitField', value: BitFieldValue}
242 - {id: 'SCG::RCCR[SCS].bitField', value: BitFieldValue}
243 - {id: 'SCG::SIRCCFG[RANGE].bitField', value: BitFieldValue}
244 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
245 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
246 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
247 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
248 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
249 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
250 sources:
251 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
252 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
253 /* clang-format on */
254
255 /*******************************************************************************
256 * Variables for BOARD_BootClockVLPR configuration
257 ******************************************************************************/
258 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR = {
259 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
260 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
261 .src = kSCG_SysClkSrcSysOsc, /* System OSC is selected as System Clock Source */
262 };
263 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR = {
264 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
265 .enableMode = kSCG_SysOscEnable |
266 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
267 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
268 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
269 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
270 };
271 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
272 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
273 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
274 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
275 };
276 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR = {
277 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
278 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
279 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
280 .trimConfig = NULL, /* Fast IRC Trim disabled */
281 };
282 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR = {
283 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
284 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
285 .range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
286 .trimConfig = NULL,
287 };
288 /*******************************************************************************
289 * Code for BOARD_BootClockVLPR configuration
290 ******************************************************************************/
BOARD_BootClockVLPR(void)291 void BOARD_BootClockVLPR(void)
292 {
293 /* Init SOSC according to board configuration. */
294 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockVLPR);
295 /* Set the XTAL0 frequency based on board settings. */
296 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockVLPR.freq);
297 /* Set SCG to SOSC mode. */
298 CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
299 /* Allow SMC all power modes. */
300 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
301 /* Set VLPR power mode. */
302 SMC_SetPowerModeVlpr(SMC);
303 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
304 {
305 }
306 /* Set SystemCoreClock variable. */
307 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
308 }
309
