1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v5.0
34 processor: MKE15Z256xxx7
35 mcu_data: ksdk2_0
36 processor_version: 0.0.17
37 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
38 /* clang-format on */
39
40 #include "clock_config.h"
41
42 /*******************************************************************************
43 * Definitions
44 ******************************************************************************/
45 #define SCG_LPFLL_DISABLE 0U /*!< LPFLL clock disabled */
46 #define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
47
48 /*******************************************************************************
49 * Variables
50 ******************************************************************************/
51 /* System clock frequency. */
52 extern uint32_t SystemCoreClock;
53
54 /*******************************************************************************
55 * Code
56 ******************************************************************************/
57 /*FUNCTION**********************************************************************
58 *
59 * Function Name : CLOCK_CONFIG_FircSafeConfig
60 * Description : This function is used to safely configure FIRC clock.
61 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
62 * Before setting FIRC, change to use SIRC as system clock,
63 * then configure FIRC. After FIRC is set, change back to use FIRC
64 * in case SIRC need to be configured.
65 * Param fircConfig : FIRC configuration.
66 *
67 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)68 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
69 {
70 scg_sys_clk_config_t curConfig;
71 const scg_sirc_config_t scgSircConfig = {
72 .enableMode = kSCG_SircEnable, .div2 = kSCG_AsyncClkDivBy2, .range = kSCG_SircRangeHigh};
73 scg_sys_clk_config_t sysClkSafeConfigSource = {
74 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
75 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
76 .src = kSCG_SysClkSrcSirc /* System clock source */
77 };
78 /* Init Sirc. */
79 CLOCK_InitSirc(&scgSircConfig);
80 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
81 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
82 /* Wait for clock source switch finished. */
83 do
84 {
85 CLOCK_GetCurSysClkConfig(&curConfig);
86 } while (curConfig.src != sysClkSafeConfigSource.src);
87
88 /* Init Firc. */
89 CLOCK_InitFirc(fircConfig);
90 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
91 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
92 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
93 /* Wait for clock source switch finished. */
94 do
95 {
96 CLOCK_GetCurSysClkConfig(&curConfig);
97 } while (curConfig.src != sysClkSafeConfigSource.src);
98 }
99
100 /*******************************************************************************
101 ************************ BOARD_InitBootClocks function ************************
102 ******************************************************************************/
BOARD_InitBootClocks(void)103 void BOARD_InitBootClocks(void)
104 {
105 BOARD_BootClockRUN();
106 }
107
108 /*******************************************************************************
109 ********************** Configuration BOARD_BootClockRUN ***********************
110 ******************************************************************************/
111 /* clang-format off */
112 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
113 !!Configuration
114 name: BOARD_BootClockRUN
115 called_from_default_init: true
116 outputs:
117 - {id: Bus_clock.outFreq, value: 24 MHz}
118 - {id: Core_clock.outFreq, value: 48 MHz}
119 - {id: Flash_clock.outFreq, value: 24 MHz}
120 - {id: LPO1KCLK.outFreq, value: 1 kHz}
121 - {id: LPO_clock.outFreq, value: 128 kHz}
122 - {id: SIRC_CLK.outFreq, value: 8 MHz}
123 - {id: System_clock.outFreq, value: 48 MHz}
124 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
125 /* clang-format on */
126
127 /*******************************************************************************
128 * Variables for BOARD_BootClockRUN configuration
129 ******************************************************************************/
130 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
131 {
132 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
133 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
134 .src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
135 };
136 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
137 {
138 .freq = 0U, /* System Oscillator frequency: 0Hz */
139 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
140 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
141 .div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
142 .workMode = kSCG_SysOscModeExt, /* Use external clock */
143 };
144 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
145 {
146 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
147 .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
148 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
149 };
150 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
151 {
152 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
153 .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
154 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
155 .trimConfig = NULL, /* Fast IRC Trim disabled */
156 };
157 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
158 {
159 .enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
160 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
161 .range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
162 .trimConfig = NULL,
163 };
164 /*******************************************************************************
165 * Code for BOARD_BootClockRUN configuration
166 ******************************************************************************/
BOARD_BootClockRUN(void)167 void BOARD_BootClockRUN(void)
168 {
169 scg_sys_clk_config_t curConfig;
170
171 /* Init FIRC. */
172 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
173 /* Init SIRC. */
174 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
175 /* Set SCG to FIRC mode. */
176 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
177 /* Wait for clock source switch finished. */
178 do
179 {
180 CLOCK_GetCurSysClkConfig(&curConfig);
181 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
182 /* Set SystemCoreClock variable. */
183 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
184 }
185
