1 /*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v5.0
34 processor: K32L3A60xxx
35 package_id: K32L3A60VPJ1A
36 mcu_data: ksdk2_0
37 processor_version: 0.0.1
38 board: FRDM-K32L3A6
39 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
40 /* clang-format on */
41
42 #include "fsl_msmc.h"
43 #include "clock_config.h"
44
45 /*******************************************************************************
46 * Definitions
47 ******************************************************************************/
48 #define SCG_LPFLL_DISABLE 0U /*!< LPFLL clock disabled */
49
50 /*******************************************************************************
51 * Variables
52 ******************************************************************************/
53 /* System clock frequency. */
54 extern uint32_t SystemCoreClock;
55
56 /*******************************************************************************
57 * Code
58 ******************************************************************************/
59 #ifndef SDK_SECONDARY_CORE
60 /*FUNCTION**********************************************************************
61 *
62 * Function Name : CLOCK_CONFIG_FircSafeConfig
63 * Description : This function is used to safely configure FIRC clock.
64 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
65 * Before setting FIRC, change to use SIRC as system clock,
66 * then configure FIRC.
67 * Param fircConfig : FIRC configuration.
68 *
69 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)70 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
71 {
72 scg_sys_clk_config_t curConfig;
73 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
74 .div1 = kSCG_AsyncClkDisable,
75 .div2 = kSCG_AsyncClkDivBy2,
76 .range = kSCG_SircRangeHigh};
77 scg_sys_clk_config_t sysClkSafeConfigSource = {
78 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
79 .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
80 .src = kSCG_SysClkSrcSirc /* System clock source. */
81 };
82 /* Init Sirc */
83 CLOCK_InitSirc(&scgSircConfig);
84 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
85 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
86 /* Wait for clock source switch finished */
87 do
88 {
89 CLOCK_GetCurSysClkConfig(&curConfig);
90 } while (curConfig.src != sysClkSafeConfigSource.src);
91
92 /* Init Firc */
93 CLOCK_InitFirc(fircConfig);
94 }
95 #endif
96
97 /*******************************************************************************
98 ************************ BOARD_InitBootClocks function ************************
99 ******************************************************************************/
BOARD_InitBootClocks(void)100 void BOARD_InitBootClocks(void)
101 {
102 BOARD_BootClockRUN();
103 }
104
105 /*******************************************************************************
106 ********************** Configuration BOARD_BootClockRUN ***********************
107 ******************************************************************************/
108 /* clang-format off */
109 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
110 !!Configuration
111 name: BOARD_BootClockRUN
112 called_from_default_init: true
113 outputs:
114 - {id: Bus_clock.outFreq, value: 48 MHz}
115 - {id: Core_clock.outFreq, value: 48 MHz}
116 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
117 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
118 - {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
119 - {id: LPO_CLK.outFreq, value: 1 kHz}
120 - {id: PCC0.PCC_LPUART0_CLK.outFreq, value: 48 MHz}
121 - {id: PCC1.PCC_LPI2C3_CLK.outFreq, value: 48 MHz}
122 - {id: Platform_clock.outFreq, value: 48 MHz}
123 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
124 - {id: Slow_clock.outFreq, value: 24 MHz}
125 - {id: System_clock.outFreq, value: 48 MHz}
126 settings:
127 - {id: PCC0.PCC_LPUART0_SEL.sel, value: SCG.FIRCDIV2_CLK}
128 - {id: PCC1.PCC_LPI2C3_SEL.sel, value: SCG.FIRCDIV2_CLK}
129 - {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
130 - {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
131 - {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
132 - {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
133 - {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
134 - {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
135 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
136 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
137 /* clang-format on */
138
139 /*******************************************************************************
140 * Variables for BOARD_BootClockRUN configuration
141 ******************************************************************************/
142 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = {
143 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
144 .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
145 .divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
146 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
147 .src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
148 };
149 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = {
150 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */
151 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
152 .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
153 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
154 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
155 };
156 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = {
157 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
158 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
159 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
160 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
161 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
162 .trimConfig = NULL,
163 };
164 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN = {
165 .enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
166 .div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
167 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
168 .div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
169 .range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
170 .trimConfig = NULL,
171 };
172 /*******************************************************************************
173 * Code for BOARD_BootClockRUN configuration
174 ******************************************************************************/
BOARD_BootClockRUN(void)175 void BOARD_BootClockRUN(void)
176 {
177 #ifndef SDK_SECONDARY_CORE
178 scg_sys_clk_config_t curConfig;
179
180 /* Init FIRC */
181 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
182 /* Set SCG to FIRC mode. */
183 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
184 /* Wait for clock source switch finished */
185 do
186 {
187 CLOCK_GetCurSysClkConfig(&curConfig);
188 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
189 /* Init SIRC */
190 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
191 /* Init LPFLL */
192 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
193 /* Set SystemCoreClock variable. */
194 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
195 /* Set PCC LPUART0 selection */
196 CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync);
197 /* Set PCC LPI2C3 selection */
198 CLOCK_SetIpSrc(kCLOCK_Lpi2c3, kCLOCK_IpSrcFircAsync);
199 #endif
200 }
201
202 /*******************************************************************************
203 ********************* Configuration BOARD_BootClockHSRUN **********************
204 ******************************************************************************/
205 /* clang-format off */
206 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
207 !!Configuration
208 name: BOARD_BootClockHSRUN
209 outputs:
210 - {id: Bus_clock.outFreq, value: 72 MHz}
211 - {id: Core_clock.outFreq, value: 72 MHz}
212 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
213 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
214 - {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
215 - {id: LPO_CLK.outFreq, value: 1 kHz}
216 - {id: Platform_clock.outFreq, value: 72 MHz}
217 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
218 - {id: Slow_clock.outFreq, value: 8 MHz}
219 - {id: System_clock.outFreq, value: 72 MHz}
220 settings:
221 - {id: SCGMode, value: LPFLL}
222 - {id: powerMode, value: HSRUN}
223 - {id: SCG.DIVCORE.scale, value: '1', locked: true}
224 - {id: SCG.DIVSLOW.scale, value: '9'}
225 - {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
226 - {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
227 - {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
228 - {id: SCG.LPFLLDIV1.scale, value: '0', locked: true}
229 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
230 - {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
231 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
232 - {id: SCG.TRIMDIV.scale, value: '24'}
233 - {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
234 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
235 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
236 /* clang-format on */
237
238 /*******************************************************************************
239 * Variables for BOARD_BootClockHSRUN configuration
240 ******************************************************************************/
241 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN = {
242 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
243 .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
244 .divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
245 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
246 .src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
247 };
248 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN = {
249 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */
250 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
251 .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
252 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
253 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
254 };
255 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN = {
256 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
257 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
258 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
259 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
260 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
261 .trimConfig = NULL,
262 };
263 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN = {
264 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
265 .div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
266 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
267 .div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
268 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
269 .trimConfig = NULL,
270 };
271 /*******************************************************************************
272 * Code for BOARD_BootClockHSRUN configuration
273 ******************************************************************************/
BOARD_BootClockHSRUN(void)274 void BOARD_BootClockHSRUN(void)
275 {
276 #ifndef SDK_SECONDARY_CORE
277 scg_sys_clk_config_t curConfig;
278
279 /* Init FIRC */
280 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
281 /* Init LPFLL */
282 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
283 #if defined(SDK_CORE_ID_CM4)
284 /* Set HSRUN power mode */
285 SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
286 SMC_SetPowerModeHsrun(SMC0);
287 while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
288 {
289 }
290 #elif defined(SDK_CORE_ID_CM0PLUS)
291 SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
292 SMC_SetPowerModeHsrun(SMC1);
293 while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
294 {
295 }
296 #endif
297 /* Set SCG to LPFLL mode. */
298 CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
299 /* Wait for clock source switch finished */
300 do
301 {
302 CLOCK_GetCurSysClkConfig(&curConfig);
303 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
304 /* Init SIRC */
305 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
306 /* Set SystemCoreClock variable. */
307 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
308 #endif
309 }
310
311 /*******************************************************************************
312 ********************* Configuration BOARD_BootClockVLPR ***********************
313 ******************************************************************************/
314 /* clang-format off */
315 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
316 !!Configuration
317 name: BOARD_BootClockVLPR
318 outputs:
319 - {id: Bus_clock.outFreq, value: 2 MHz}
320 - {id: Core_clock.outFreq, value: 4 MHz}
321 - {id: LPO_CLK.outFreq, value: 1 kHz}
322 - {id: Platform_clock.outFreq, value: 4 MHz}
323 - {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
324 - {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
325 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
326 - {id: Slow_clock.outFreq, value: 4000/9 kHz}
327 - {id: System_clock.outFreq, value: 4 MHz}
328 settings:
329 - {id: SCGMode, value: SIRC}
330 - {id: powerMode, value: VLPR}
331 - {id: SCG.DIVBUS.scale, value: '2', locked: true}
332 - {id: SCG.DIVCORE.scale, value: '2', locked: true}
333 - {id: SCG.DIVSLOW.scale, value: '9'}
334 - {id: SCG.FIRCDIV1.scale, value: '1'}
335 - {id: SCG.SCSSEL.sel, value: SCG.SIRC}
336 - {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
337 - {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
338 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
339 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
340 /* clang-format on */
341
342 /*******************************************************************************
343 * Variables for BOARD_BootClockVLPR configuration
344 ******************************************************************************/
345 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR = {
346 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
347 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
348 .divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
349 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
350 .src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
351 };
352 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
353 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower, /* Enable SIRC clock, Enable SIRC in low power mode */
354 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
355 .div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
356 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
357 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
358 };
359 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR = {
360 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
361 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
362 .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
363 .div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
364 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
365 .trimConfig = NULL,
366 };
367 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR = {
368 .enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
369 .div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
370 .div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
371 .div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
372 .range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
373 .trimConfig = NULL,
374 };
375 /*******************************************************************************
376 * Code for BOARD_BootClockVLPR configuration
377 ******************************************************************************/
BOARD_BootClockVLPR(void)378 void BOARD_BootClockVLPR(void)
379 {
380 #ifndef SDK_SECONDARY_CORE
381 scg_sys_clk_config_t curConfig;
382
383 /* Init SIRC */
384 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
385 /* Set SCG to SIRC mode. */
386 CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
387 /* Init FIRC */
388 CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
389 /* Init LPFLL */
390 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
391 #if defined(SDK_CORE_ID_CM4)
392 /* Set VLPR power mode. */
393 SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
394 SMC_SetPowerModeVlpr(SMC0);
395 while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
396 {
397 }
398 #elif defined(SDK_CORE_ID_CM0PLUS)
399 /* Set VLPR power mode. */
400 SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
401 SMC_SetPowerModeVlpr(SMC1);
402 while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
403 {
404 }
405 #endif
406 /* Wait for clock source switch finished */
407 do
408 {
409 CLOCK_GetCurSysClkConfig(&curConfig);
410 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
411 /* Set SystemCoreClock variable. */
412 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
413 #endif
414 }
415
