1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v4.1
34 processor: MKE18F512xxx16
35 package_id: MKE18F512VLL16
36 mcu_data: ksdk2_0
37 processor_version: 4.0.0
38 board: TWR-KE18F
39 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
40 /* clang-format on */
41
42 #include "fsl_smc.h"
43 #include "clock_config.h"
44
45 /*******************************************************************************
46 * Definitions
47 ******************************************************************************/
48
49 /*******************************************************************************
50 * Variables
51 ******************************************************************************/
52 /* System clock frequency. */
53 extern uint32_t SystemCoreClock;
54
55 /*******************************************************************************
56 * Code
57 ******************************************************************************/
58 /*FUNCTION**********************************************************************
59 *
60 * Function Name : CLOCK_CONFIG_FircSafeConfig
61 * Description : This function is used to safely configure FIRC clock.
62 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
63 * Before setting FIRC, change to use SIRC as system clock,
64 * then configure FIRC. After FIRC is set, change back to use FIRC
65 * in case SIRC need to be configured.
66 * Param fircConfig : FIRC configuration.
67 *
68 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)69 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
70 {
71 scg_sys_clk_config_t curConfig;
72 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
73 .div1 = kSCG_AsyncClkDisable,
74 .div2 = kSCG_AsyncClkDivBy2,
75 .range = kSCG_SircRangeHigh};
76 scg_sys_clk_config_t sysClkSafeConfigSource = {
77 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
78 .divBus = kSCG_SysClkDivBy1, /* Bus clock divider */
79 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
80 .src = kSCG_SysClkSrcSirc /* System clock source */
81 };
82 /* Init Sirc. */
83 CLOCK_InitSirc(&scgSircConfig);
84 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
85 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
86 /* Wait for clock source switch finished. */
87 do
88 {
89 CLOCK_GetCurSysClkConfig(&curConfig);
90 } while (curConfig.src != sysClkSafeConfigSource.src);
91
92 /* Init Firc. */
93 CLOCK_InitFirc(fircConfig);
94 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
95 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
96 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
97 /* Wait for clock source switch finished. */
98 do
99 {
100 CLOCK_GetCurSysClkConfig(&curConfig);
101 } while (curConfig.src != sysClkSafeConfigSource.src);
102 }
103
104 /*******************************************************************************
105 ************************ BOARD_InitBootClocks function ************************
106 ******************************************************************************/
BOARD_InitBootClocks(void)107 void BOARD_InitBootClocks(void)
108 {
109 BOARD_BootClockHSRUN();
110 }
111
112 /*******************************************************************************
113 ********************* Configuration BOARD_BootClockVLPR ***********************
114 ******************************************************************************/
115 /* clang-format off */
116 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
117 !!Configuration
118 name: BOARD_BootClockVLPR
119 outputs:
120 - {id: Bus_clock.outFreq, value: 2 MHz}
121 - {id: Core_clock.outFreq, value: 4 MHz}
122 - {id: Flash_clock.outFreq, value: 1 MHz}
123 - {id: LPO1KCLK.outFreq, value: 1 kHz}
124 - {id: LPO_clock.outFreq, value: 128 kHz}
125 - {id: SOSCDIV1_CLK.outFreq, value: 8 MHz}
126 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
127 - {id: SOSC_CLK.outFreq, value: 8 MHz}
128 - {id: System_clock.outFreq, value: 4 MHz}
129 settings:
130 - {id: SCGMode, value: SOSC}
131 - {id: powerMode, value: VLPR}
132 - {id: SCG.DIVBUS.scale, value: '2'}
133 - {id: SCG.DIVCORE.scale, value: '2'}
134 - {id: SCG.DIVSLOW.scale, value: '4'}
135 - {id: SCG.FIRCDIV1.scale, value: '1'}
136 - {id: SCG.FIRCDIV2.scale, value: '1'}
137 - {id: SCG.SCSSEL.sel, value: SCG.SOSC}
138 - {id: SCG.SIRCDIV1.scale, value: '1'}
139 - {id: SCG.SIRCDIV2.scale, value: '2'}
140 - {id: SCG.SOSCDIV1.scale, value: '1'}
141 - {id: SCG.SOSCDIV2.scale, value: '1'}
142 - {id: SCG.SPLLDIV1.scale, value: '1'}
143 - {id: SCG.SPLLDIV2.scale, value: '2'}
144 - {id: SCG.SPLL_mul.scale, value: '30'}
145 - {id: 'SCG::FIRCCFG[RANGE].bitField', value: BitFieldValue}
146 - {id: 'SCG::RCCR[DIVBUS].bitField', value: BitFieldValue}
147 - {id: 'SCG::RCCR[DIVCORE].bitField', value: BitFieldValue}
148 - {id: 'SCG::RCCR[DIVSLOW].bitField', value: BitFieldValue}
149 - {id: 'SCG::RCCR[SCS].bitField', value: BitFieldValue}
150 - {id: 'SCG::SIRCCFG[RANGE].bitField', value: BitFieldValue}
151 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
152 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
153 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
154 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
155 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
156 - {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
157 sources:
158 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
159 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
160 /* clang-format on */
161
162 /*******************************************************************************
163 * Variables for BOARD_BootClockVLPR configuration
164 ******************************************************************************/
165 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR = {
166 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
167 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
168 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
169 .src = kSCG_SysClkSrcSysOsc, /* System OSC is selected as System Clock Source */
170 };
171 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR = {
172 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
173 .enableMode = kSCG_SysOscEnable |
174 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
175 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
176 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
177 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
178 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
179 };
180 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
181 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
182 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
183 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
184 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
185 };
186 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR = {
187 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
188 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
189 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
190 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
191 .trimConfig = NULL, /* Fast IRC Trim disabled */
192 };
193 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR = {
194 .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
195 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
196 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
197 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
198 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
199 .prediv = 0, /* Divided by 1 */
200 .mult = 14, /* Multiply Factor is 30 */
201 };
202 /*******************************************************************************
203 * Code for BOARD_BootClockVLPR configuration
204 ******************************************************************************/
BOARD_BootClockVLPR(void)205 void BOARD_BootClockVLPR(void)
206 {
207 /* Init SOSC according to board configuration. */
208 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockVLPR);
209 /* Set the XTAL0 frequency based on board settings. */
210 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockVLPR.freq);
211 /* Set SCG to SOSC mode. */
212 CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
213 /* Allow SMC all power modes. */
214 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
215 /* Set VLPR power mode. */
216 SMC_SetPowerModeVlpr(SMC);
217 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
218 {
219 }
220 /* Set SystemCoreClock variable. */
221 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
222 }
223
224 /*******************************************************************************
225 ********************** Configuration BOARD_BootClockRUN ***********************
226 ******************************************************************************/
227 /* clang-format off */
228 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
229 !!Configuration
230 name: BOARD_BootClockRUN
231 outputs:
232 - {id: Bus_clock.outFreq, value: 60 MHz}
233 - {id: Core_clock.outFreq, value: 120 MHz}
234 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
235 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
236 - {id: Flash_clock.outFreq, value: 24 MHz}
237 - {id: LPO1KCLK.outFreq, value: 1 kHz}
238 - {id: LPO_clock.outFreq, value: 128 kHz}
239 - {id: PLLDIV1_CLK.outFreq, value: 120 MHz}
240 - {id: PLLDIV2_CLK.outFreq, value: 60 MHz}
241 - {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
242 - {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
243 - {id: SIRC_CLK.outFreq, value: 8 MHz}
244 - {id: SOSCDIV1_CLK.outFreq, value: 8 MHz}
245 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
246 - {id: SOSC_CLK.outFreq, value: 8 MHz}
247 - {id: System_clock.outFreq, value: 120 MHz}
248 settings:
249 - {id: SCGMode, value: SPLL}
250 - {id: SCG.DIVBUS.scale, value: '2'}
251 - {id: SCG.DIVSLOW.scale, value: '5'}
252 - {id: SCG.FIRCDIV1.scale, value: '1'}
253 - {id: SCG.FIRCDIV2.scale, value: '1'}
254 - {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
255 - {id: SCG.SIRCDIV1.scale, value: '1'}
256 - {id: SCG.SIRCDIV2.scale, value: '2'}
257 - {id: SCG.SOSCDIV1.scale, value: '1'}
258 - {id: SCG.SOSCDIV2.scale, value: '1'}
259 - {id: SCG.SPLLDIV1.scale, value: '1'}
260 - {id: SCG.SPLLDIV2.scale, value: '2'}
261 - {id: SCG.SPLL_mul.scale, value: '30'}
262 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
263 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
264 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
265 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
266 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
267 - {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
268 sources:
269 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
270 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
271 /* clang-format on */
272
273 /*******************************************************************************
274 * Variables for BOARD_BootClockRUN configuration
275 ******************************************************************************/
276 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = {
277 .divSlow = kSCG_SysClkDivBy5, /* Slow Clock Divider: divided by 5 */
278 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
279 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
280 .src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
281 };
282 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = {
283 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
284 .enableMode = kSCG_SysOscEnable |
285 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
286 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
287 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
288 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
289 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
290 };
291 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = {
292 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
293 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
294 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
295 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
296 };
297 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = {
298 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
299 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
300 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
301 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
302 .trimConfig = NULL, /* Fast IRC Trim disabled */
303 };
304 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN = {
305 .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
306 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
307 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
308 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
309 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
310 .prediv = 0, /* Divided by 1 */
311 .mult = 14, /* Multiply Factor is 30 */
312 };
313 /*******************************************************************************
314 * Code for BOARD_BootClockRUN configuration
315 ******************************************************************************/
BOARD_BootClockRUN(void)316 void BOARD_BootClockRUN(void)
317 {
318 scg_sys_clk_config_t curConfig;
319
320 /* Init SOSC according to board configuration. */
321 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
322 /* Set the XTAL0 frequency based on board settings. */
323 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
324 /* Init FIRC. */
325 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
326 /* Init SIRC. */
327 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
328 /* Init SysPll. */
329 CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockRUN);
330 /* Set SCG to SPLL mode. */
331 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
332 /* Wait for clock source switch finished. */
333 do
334 {
335 CLOCK_GetCurSysClkConfig(&curConfig);
336 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
337 /* Set SystemCoreClock variable. */
338 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
339 }
340
341 /*******************************************************************************
342 ********************* Configuration BOARD_BootClockHSRUN **********************
343 ******************************************************************************/
344 /* clang-format off */
345 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
346 !!Configuration
347 name: BOARD_BootClockHSRUN
348 called_from_default_init: true
349 outputs:
350 - {id: Bus_clock.outFreq, value: 84 MHz}
351 - {id: Core_clock.outFreq, value: 168 MHz}
352 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
353 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
354 - {id: Flash_clock.outFreq, value: 24 MHz}
355 - {id: LPO1KCLK.outFreq, value: 1 kHz}
356 - {id: LPO_clock.outFreq, value: 128 kHz}
357 - {id: PLLDIV1_CLK.outFreq, value: 168 MHz}
358 - {id: PLLDIV2_CLK.outFreq, value: 84 MHz}
359 - {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
360 - {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
361 - {id: SIRC_CLK.outFreq, value: 8 MHz}
362 - {id: SOSCDIV1_CLK.outFreq, value: 8 MHz}
363 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
364 - {id: SOSC_CLK.outFreq, value: 8 MHz}
365 - {id: System_clock.outFreq, value: 168 MHz}
366 settings:
367 - {id: SCGMode, value: SPLL}
368 - {id: powerMode, value: HSRUN}
369 - {id: SCG.DIVBUS.scale, value: '2'}
370 - {id: SCG.DIVSLOW.scale, value: '7'}
371 - {id: SCG.FIRCDIV1.scale, value: '1'}
372 - {id: SCG.FIRCDIV2.scale, value: '1'}
373 - {id: SCG.PREDIV.scale, value: '6'}
374 - {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
375 - {id: SCG.SIRCDIV1.scale, value: '1'}
376 - {id: SCG.SIRCDIV2.scale, value: '2'}
377 - {id: SCG.SOSCDIV1.scale, value: '1'}
378 - {id: SCG.SOSCDIV2.scale, value: '1'}
379 - {id: SCG.SPLLDIV1.scale, value: '1'}
380 - {id: SCG.SPLLDIV2.scale, value: '2'}
381 - {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
382 - {id: SCG.SPLL_mul.scale, value: '42'}
383 - {id: 'SCG::RCCR[DIVBUS].bitField', value: BitFieldValue}
384 - {id: 'SCG::RCCR[DIVCORE].bitField', value: BitFieldValue}
385 - {id: 'SCG::RCCR[DIVSLOW].bitField', value: BitFieldValue}
386 - {id: 'SCG::RCCR[SCS].bitField', value: BitFieldValue}
387 - {id: 'SCG::VCCR[DIVBUS].bitField', value: BitFieldValue}
388 - {id: 'SCG::VCCR[DIVCORE].bitField', value: BitFieldValue}
389 - {id: 'SCG::VCCR[DIVSLOW].bitField', value: BitFieldValue}
390 - {id: 'SCG::VCCR[SCS].bitField', value: BitFieldValue}
391 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
392 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
393 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
394 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
395 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
396 - {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
397 sources:
398 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
399 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
400 /* clang-format on */
401
402 /*******************************************************************************
403 * Variables for BOARD_BootClockHSRUN configuration
404 ******************************************************************************/
405 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN = {
406 .divSlow = kSCG_SysClkDivBy7, /* Slow Clock Divider: divided by 7 */
407 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
408 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
409 .src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
410 };
411 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN = {
412 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
413 .enableMode = kSCG_SysOscEnable |
414 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
415 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
416 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
417 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
418 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
419 };
420 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN = {
421 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
422 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
423 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
424 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
425 };
426 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN = {
427 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
428 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
429 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
430 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
431 .trimConfig = NULL, /* Fast IRC Trim disabled */
432 };
433 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN = {
434 .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
435 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
436 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
437 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
438 .src = kSCG_SysPllSrcFirc, /* System PLL clock source is Fast IRC */
439 .prediv = 5, /* Divided by 6 */
440 .mult = 26, /* Multiply Factor is 42 */
441 };
442 /*******************************************************************************
443 * Code for BOARD_BootClockHSRUN configuration
444 ******************************************************************************/
BOARD_BootClockHSRUN(void)445 void BOARD_BootClockHSRUN(void)
446 {
447 scg_sys_clk_config_t curConfig;
448
449 /* Init SOSC according to board configuration. */
450 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
451 /* Set the XTAL0 frequency based on board settings. */
452 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
453 /* Init FIRC. */
454 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
455 /* Set HSRUN power mode. */
456 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
457 SMC_SetPowerModeHsrun(SMC);
458 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
459 {
460 }
461
462 /* Init SIRC. */
463 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
464 /* Init SysPll. */
465 CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
466 /* Set SCG to SPLL mode. */
467 CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
468 /* Wait for clock source switch finished. */
469 do
470 {
471 CLOCK_GetCurSysClkConfig(&curConfig);
472 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
473 /* Set SystemCoreClock variable. */
474 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
475 }
476
