1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v5.0
34 processor: MKE18F512xxx16
35 mcu_data: ksdk2_0
36 processor_version: 0.0.17
37 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
38 /* clang-format on */
39
40 #include "clock_config.h"
41
42 /*******************************************************************************
43 * Definitions
44 ******************************************************************************/
45 #define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
46 #define SCG_SPLL_DISABLE 0U /*!< System PLL disabled */
47
48 /*******************************************************************************
49 * Variables
50 ******************************************************************************/
51 /* System clock frequency. */
52 extern uint32_t SystemCoreClock;
53
54 /*******************************************************************************
55 * Code
56 ******************************************************************************/
57 /*FUNCTION**********************************************************************
58 *
59 * Function Name : CLOCK_CONFIG_FircSafeConfig
60 * Description : This function is used to safely configure FIRC clock.
61 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
62 * Before setting FIRC, change to use SIRC as system clock,
63 * then configure FIRC. After FIRC is set, change back to use FIRC
64 * in case SIRC need to be configured.
65 * Param fircConfig : FIRC configuration.
66 *
67 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)68 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
69 {
70 scg_sys_clk_config_t curConfig;
71 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
72 .div1 = kSCG_AsyncClkDisable,
73 .div2 = kSCG_AsyncClkDivBy2,
74 .range = kSCG_SircRangeHigh};
75 scg_sys_clk_config_t sysClkSafeConfigSource = {
76 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
77 .divBus = kSCG_SysClkDivBy1, /* Bus clock divider */
78 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
79 .src = kSCG_SysClkSrcSirc /* System clock source */
80 };
81 /* Init Sirc. */
82 CLOCK_InitSirc(&scgSircConfig);
83 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
84 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
85 /* Wait for clock source switch finished. */
86 do
87 {
88 CLOCK_GetCurSysClkConfig(&curConfig);
89 } while (curConfig.src != sysClkSafeConfigSource.src);
90
91 /* Init Firc. */
92 CLOCK_InitFirc(fircConfig);
93 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
94 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
95 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
96 /* Wait for clock source switch finished. */
97 do
98 {
99 CLOCK_GetCurSysClkConfig(&curConfig);
100 } while (curConfig.src != sysClkSafeConfigSource.src);
101 }
102
103 /*******************************************************************************
104 ************************ BOARD_InitBootClocks function ************************
105 ******************************************************************************/
BOARD_InitBootClocks(void)106 void BOARD_InitBootClocks(void)
107 {
108 BOARD_BootClockRUN();
109 }
110
111 /*******************************************************************************
112 ********************** Configuration BOARD_BootClockRUN ***********************
113 ******************************************************************************/
114 /* clang-format off */
115 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
116 !!Configuration
117 name: BOARD_BootClockRUN
118 called_from_default_init: true
119 outputs:
120 - {id: Bus_clock.outFreq, value: 48 MHz}
121 - {id: Core_clock.outFreq, value: 48 MHz}
122 - {id: Flash_clock.outFreq, value: 24 MHz}
123 - {id: LPO1KCLK.outFreq, value: 1 kHz}
124 - {id: LPO_clock.outFreq, value: 128 kHz}
125 - {id: SIRC_CLK.outFreq, value: 8 MHz}
126 - {id: System_clock.outFreq, value: 48 MHz}
127 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
128 /* clang-format on */
129
130 /*******************************************************************************
131 * Variables for BOARD_BootClockRUN configuration
132 ******************************************************************************/
133 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
134 {
135 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
136 .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
137 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
138 .src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
139 };
140 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
141 {
142 .freq = 0U, /* System Oscillator frequency: 0Hz */
143 .enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
144 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
145 .div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
146 .div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
147 .workMode = kSCG_SysOscModeExt, /* Use external clock */
148 };
149 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
150 {
151 .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
152 .div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
153 .div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
154 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
155 };
156 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
157 {
158 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
159 .div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
160 .div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
161 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
162 .trimConfig = NULL, /* Fast IRC Trim disabled */
163 };
164 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN =
165 {
166 .enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
167 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
168 .div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
169 .div2 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 2: Clock output is disabled */
170 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
171 .prediv = 0, /* Divided by 1 */
172 .mult = 0, /* Multiply Factor is 16 */
173 };
174 /*******************************************************************************
175 * Code for BOARD_BootClockRUN configuration
176 ******************************************************************************/
BOARD_BootClockRUN(void)177 void BOARD_BootClockRUN(void)
178 {
179 scg_sys_clk_config_t curConfig;
180
181 /* Init FIRC. */
182 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
183 /* Init SIRC. */
184 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
185 /* Set SCG to FIRC mode. */
186 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
187 /* Wait for clock source switch finished. */
188 do
189 {
190 CLOCK_GetCurSysClkConfig(&curConfig);
191 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
192 /* Set SystemCoreClock variable. */
193 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
194 }
195
196
