1 /*
2 * Copyright 2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 /***********************************************************************************************************************
8 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
9 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
10 **********************************************************************************************************************/
11 /*
12 * How to setup clock using clock driver functions:
13 *
14 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
15 * Note: The clock could not be set when it is being used as system clock.
16 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
17 * so before setting FIRC, change to use another avaliable clock source.
18 *
19 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
20 *
21 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
22 * Wait until the system clock source is changed to target source.
23 *
24 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
25 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
26 * Supported run mode and clock restrictions could be found in Reference Manual.
27 */
28
29 /* clang-format off */
30 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
31 !!GlobalInfo
32 product: Clocks v9.0
33 processor: MKE17Z256xxx7
34 package_id: MKE17Z256VLL7
35 mcu_data: ksdk2_0
36 processor_version: 0.7.1
37 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
38 /* clang-format on */
39
40 #include "fsl_smc.h"
41 #include "clock_config.h"
42
43 /*******************************************************************************
44 * Definitions
45 ******************************************************************************/
46
47 /*******************************************************************************
48 * Variables
49 ******************************************************************************/
50 /* System clock frequency. */
51 extern uint32_t SystemCoreClock;
52
53 /*******************************************************************************
54 * Code
55 ******************************************************************************/
56 /*FUNCTION**********************************************************************
57 *
58 * Function Name : CLOCK_CONFIG_FircSafeConfig
59 * Description : This function is used to safely configure FIRC clock.
60 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
61 * Before setting FIRC, change to use SIRC as system clock,
62 * then configure FIRC. After FIRC is set, change back to use FIRC
63 * in case SIRC need to be configured.
64 * Param fircConfig : FIRC configuration.
65 *
66 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)67 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
68 {
69 scg_sys_clk_config_t curConfig;
70 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
71 .div2 = kSCG_AsyncClkDivBy2,
72 .range = kSCG_SircRangeHigh};
73 scg_sys_clk_config_t sysClkSafeConfigSource = {
74 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
75 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
76 .src = kSCG_SysClkSrcSirc /* System clock source */
77 };
78 /* Init Sirc. */
79 CLOCK_InitSirc(&scgSircConfig);
80 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
81 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
82 /* Wait for clock source switch finished. */
83 do
84 {
85 CLOCK_GetCurSysClkConfig(&curConfig);
86 } while (curConfig.src != sysClkSafeConfigSource.src);
87
88 /* Init Firc. */
89 CLOCK_InitFirc(fircConfig);
90 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
91 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
92 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
93 /* Wait for clock source switch finished. */
94 do
95 {
96 CLOCK_GetCurSysClkConfig(&curConfig);
97 } while (curConfig.src != sysClkSafeConfigSource.src);
98 }
99
100 /*******************************************************************************
101 ************************ BOARD_InitBootClocks function ************************
102 ******************************************************************************/
BOARD_InitBootClocks(void)103 void BOARD_InitBootClocks(void)
104 {
105 BOARD_BootClockRUN();
106 }
107
108 /*******************************************************************************
109 ********************** Configuration BOARD_BootClockRUN ***********************
110 ******************************************************************************/
111 /* clang-format off */
112 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
113 !!Configuration
114 name: BOARD_BootClockRUN
115 called_from_default_init: true
116 outputs:
117 - {id: Bus_clock.outFreq, value: 24 MHz}
118 - {id: Core_clock.outFreq, value: 72 MHz}
119 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
120 - {id: FLLDIV2_CLK.outFreq, value: 36 MHz}
121 - {id: Flash_clock.outFreq, value: 24 MHz}
122 - {id: LPO1KCLK.outFreq, value: 1 kHz}
123 - {id: LPO_clock.outFreq, value: 128 kHz}
124 - {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
125 - {id: SIRC_CLK.outFreq, value: 8 MHz}
126 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
127 - {id: SOSC_CLK.outFreq, value: 8 MHz}
128 - {id: System_clock.outFreq, value: 72 MHz}
129 settings:
130 - {id: SCGMode, value: LPFLL}
131 - {id: OSC32_CR_ROSCE_CFG, value: Enabled}
132 - {id: SCG.DIVCORE.scale, value: '1', locked: true}
133 - {id: SCG.DIVSLOW.scale, value: '3', locked: true}
134 - {id: SCG.FIRCDIV2.scale, value: '1'}
135 - {id: SCG.LPFLLDIV2.scale, value: '2'}
136 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
137 - {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
138 - {id: SCG.SIRCDIV2.scale, value: '2'}
139 - {id: SCG.SOSCDIV2.scale, value: '1'}
140 - {id: SCG.TRIMDIV.scale, value: '4'}
141 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
142 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
143 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
144 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
145 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
146 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
147 sources:
148 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
149 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
150 /* clang-format on */
151
152 /*******************************************************************************
153 * Variables for BOARD_BootClockRUN configuration
154 ******************************************************************************/
155 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = {
156 .divSlow = kSCG_SysClkDivBy3, /* Slow Clock Divider: divided by 3 */
157 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
158 .src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
159 };
160 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = {
161 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
162 .enableMode = kSCG_SysOscEnable |
163 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
164 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
165 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
166 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
167 };
168 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = {
169 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
170 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
171 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
172 };
173 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = {
174 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
175 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
176 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
177 .trimConfig = NULL, /* Fast IRC Trim disabled */
178 };
179 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN = {
180 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
181 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
182 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
183 .trimConfig = NULL,
184 };
185 /*******************************************************************************
186 * Code for BOARD_BootClockRUN configuration
187 ******************************************************************************/
BOARD_BootClockRUN(void)188 void BOARD_BootClockRUN(void)
189 {
190 scg_sys_clk_config_t curConfig;
191
192 /* Init SOSC according to board configuration. */
193 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
194 /* Set the XTAL0 frequency based on board settings. */
195 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
196 /* Init FIRC. */
197 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
198 /* Init SIRC. */
199 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
200 /* Init LPFLL. */
201 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
202 /* Set SCG to LPFLL mode. */
203 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
204 /* Wait for clock source switch finished. */
205 do
206 {
207 CLOCK_GetCurSysClkConfig(&curConfig);
208 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
209 /* Set SystemCoreClock variable. */
210 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
211 }
212
213 /*******************************************************************************
214 ********************* Configuration BOARD_BootClockVLPR ***********************
215 ******************************************************************************/
216 /* clang-format off */
217 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
218 !!Configuration
219 name: BOARD_BootClockVLPR
220 outputs:
221 - {id: Bus_clock.outFreq, value: 1 MHz}
222 - {id: Core_clock.outFreq, value: 4 MHz}
223 - {id: Flash_clock.outFreq, value: 1 MHz}
224 - {id: LPO1KCLK.outFreq, value: 1 kHz}
225 - {id: LPO_clock.outFreq, value: 128 kHz}
226 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
227 - {id: SOSC_CLK.outFreq, value: 8 MHz}
228 - {id: System_clock.outFreq, value: 4 MHz}
229 settings:
230 - {id: SCGMode, value: SOSC}
231 - {id: powerMode, value: VLPR}
232 - {id: OSC32_CR_ROSCE_CFG, value: Enabled}
233 - {id: SCG.DIVCORE.scale, value: '2', locked: true}
234 - {id: SCG.DIVSLOW.scale, value: '4', locked: true}
235 - {id: SCG.FIRCDIV2.scale, value: '1'}
236 - {id: SCG.LPFLLDIV2.scale, value: '2'}
237 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
238 - {id: SCG.SCSSEL.sel, value: SCG.SOSC}
239 - {id: SCG.SIRCDIV2.scale, value: '2'}
240 - {id: SCG.SOSCDIV2.scale, value: '1'}
241 - {id: SCG.TRIMDIV.scale, value: '4'}
242 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
243 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
244 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
245 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
246 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
247 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
248 sources:
249 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
250 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
251 /* clang-format on */
252
253 /*******************************************************************************
254 * Variables for BOARD_BootClockVLPR configuration
255 ******************************************************************************/
256 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR = {
257 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
258 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
259 .src = kSCG_SysClkSrcSysOsc, /* System OSC is selected as System Clock Source */
260 };
261 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR = {
262 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
263 .enableMode = kSCG_SysOscEnable |
264 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
265 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
266 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
267 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
268 };
269 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
270 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
271 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
272 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
273 };
274 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR = {
275 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
276 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
277 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
278 .trimConfig = NULL, /* Fast IRC Trim disabled */
279 };
280 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR = {
281 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
282 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
283 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
284 .trimConfig = NULL,
285 };
286 /*******************************************************************************
287 * Code for BOARD_BootClockVLPR configuration
288 ******************************************************************************/
BOARD_BootClockVLPR(void)289 void BOARD_BootClockVLPR(void)
290 {
291 /* Init SOSC according to board configuration. */
292 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockVLPR);
293 /* Set the XTAL0 frequency based on board settings. */
294 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockVLPR.freq);
295 /* Set SCG to SOSC mode. */
296 CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
297 /* Allow SMC all power modes. */
298 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
299 /* Set VLPR power mode. */
300 SMC_SetPowerModeVlpr(SMC);
301 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
302 {
303 }
304 /* Set SystemCoreClock variable. */
305 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
306 }
307
