1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019,2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 /***********************************************************************************************************************
10 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
11 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
12 **********************************************************************************************************************/
13 /*
14 * How to setup clock using clock driver functions:
15 *
16 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
17 * Note: The clock could not be set when it is being used as system clock.
18 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
19 * so before setting FIRC, change to use another avaliable clock source.
20 *
21 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
22 *
23 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
24 * Wait until the system clock source is changed to target source.
25 *
26 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
27 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
28 * Supported run mode and clock restrictions could be found in Reference Manual.
29 */
30
31 /* clang-format off */
32 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
33 !!GlobalInfo
34 product: Clocks v8.0
35 processor: MKE15Z256xxx7
36 package_id: MKE15Z256VLL7
37 mcu_data: ksdk2_0
38 processor_version: 0.10.10
39 board: FRDM-KE15Z
40 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
41 /* clang-format on */
42
43 #include "fsl_smc.h"
44 #include "clock_config.h"
45
46 /*******************************************************************************
47 * Definitions
48 ******************************************************************************/
49
50 /*******************************************************************************
51 * Variables
52 ******************************************************************************/
53 /* System clock frequency. */
54 extern uint32_t SystemCoreClock;
55
56 /*******************************************************************************
57 * Code
58 ******************************************************************************/
59 /*FUNCTION**********************************************************************
60 *
61 * Function Name : CLOCK_CONFIG_FircSafeConfig
62 * Description : This function is used to safely configure FIRC clock.
63 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
64 * Before setting FIRC, change to use SIRC as system clock,
65 * then configure FIRC. After FIRC is set, change back to use FIRC
66 * in case SIRC need to be configured.
67 * Param fircConfig : FIRC configuration.
68 *
69 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)70 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
71 {
72 scg_sys_clk_config_t curConfig;
73 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
74 .div2 = kSCG_AsyncClkDivBy2,
75 .range = kSCG_SircRangeHigh};
76 scg_sys_clk_config_t sysClkSafeConfigSource = {
77 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
78 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
79 .src = kSCG_SysClkSrcSirc /* System clock source */
80 };
81 /* Init Sirc. */
82 CLOCK_InitSirc(&scgSircConfig);
83 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
84 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
85 /* Wait for clock source switch finished. */
86 do
87 {
88 CLOCK_GetCurSysClkConfig(&curConfig);
89 } while (curConfig.src != sysClkSafeConfigSource.src);
90
91 /* Init Firc. */
92 CLOCK_InitFirc(fircConfig);
93 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
94 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
95 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
96 /* Wait for clock source switch finished. */
97 do
98 {
99 CLOCK_GetCurSysClkConfig(&curConfig);
100 } while (curConfig.src != sysClkSafeConfigSource.src);
101 }
102
103 /*******************************************************************************
104 ************************ BOARD_InitBootClocks function ************************
105 ******************************************************************************/
BOARD_InitBootClocks(void)106 void BOARD_InitBootClocks(void)
107 {
108 BOARD_BootClockRUN();
109 }
110
111 /*******************************************************************************
112 ********************** Configuration BOARD_BootClockRUN ***********************
113 ******************************************************************************/
114 /* clang-format off */
115 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
116 !!Configuration
117 name: BOARD_BootClockRUN
118 called_from_default_init: true
119 outputs:
120 - {id: Bus_clock.outFreq, value: 24 MHz}
121 - {id: Core_clock.outFreq, value: 72 MHz}
122 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
123 - {id: FLLDIV2_CLK.outFreq, value: 36 MHz}
124 - {id: Flash_clock.outFreq, value: 24 MHz}
125 - {id: LPO1KCLK.outFreq, value: 1 kHz}
126 - {id: LPO_clock.outFreq, value: 128 kHz}
127 - {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
128 - {id: SIRC_CLK.outFreq, value: 8 MHz}
129 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
130 - {id: SOSC_CLK.outFreq, value: 8 MHz}
131 - {id: System_clock.outFreq, value: 72 MHz}
132 settings:
133 - {id: SCGMode, value: LPFLL}
134 - {id: OSC32_CR_ROSCE_CFG, value: Enabled}
135 - {id: SCG.DIVCORE.scale, value: '1', locked: true}
136 - {id: SCG.DIVSLOW.scale, value: '3', locked: true}
137 - {id: SCG.FIRCDIV2.scale, value: '1'}
138 - {id: SCG.LPFLLDIV2.scale, value: '2'}
139 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
140 - {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
141 - {id: SCG.SIRCDIV2.scale, value: '2'}
142 - {id: SCG.SOSCDIV2.scale, value: '1'}
143 - {id: SCG.TRIMDIV.scale, value: '4'}
144 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
145 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
146 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
147 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
148 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
149 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
150 sources:
151 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
152 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
153 /* clang-format on */
154
155 /*******************************************************************************
156 * Variables for BOARD_BootClockRUN configuration
157 ******************************************************************************/
158 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
159 {
160 .divSlow = kSCG_SysClkDivBy3, /* Slow Clock Divider: divided by 3 */
161 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
162 .src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
163 };
164 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
165 {
166 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
167 .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,/* Enable System OSC clock, Enable System OSC in low power mode */
168 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
169 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
170 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
171 };
172 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
173 {
174 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
175 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
176 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
177 };
178 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
179 {
180 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
181 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
182 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
183 .trimConfig = NULL, /* Fast IRC Trim disabled */
184 };
185 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
186 {
187 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
188 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
189 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
190 .trimConfig = NULL,
191 };
192 /*******************************************************************************
193 * Code for BOARD_BootClockRUN configuration
194 ******************************************************************************/
BOARD_BootClockRUN(void)195 void BOARD_BootClockRUN(void)
196 {
197 scg_sys_clk_config_t curConfig;
198
199 /* Init SOSC according to board configuration. */
200 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
201 /* Set the XTAL0 frequency based on board settings. */
202 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
203 /* Init FIRC. */
204 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
205 /* Init SIRC. */
206 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
207 /* Init LPFLL. */
208 CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
209 /* Set SCG to LPFLL mode. */
210 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
211 /* Wait for clock source switch finished. */
212 do
213 {
214 CLOCK_GetCurSysClkConfig(&curConfig);
215 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
216 /* Set SystemCoreClock variable. */
217 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
218 }
219
220 /*******************************************************************************
221 ********************* Configuration BOARD_BootClockVLPR ***********************
222 ******************************************************************************/
223 /* clang-format off */
224 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
225 !!Configuration
226 name: BOARD_BootClockVLPR
227 outputs:
228 - {id: Bus_clock.outFreq, value: 1 MHz}
229 - {id: Core_clock.outFreq, value: 4 MHz}
230 - {id: Flash_clock.outFreq, value: 1 MHz}
231 - {id: LPO1KCLK.outFreq, value: 1 kHz}
232 - {id: LPO_clock.outFreq, value: 128 kHz}
233 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
234 - {id: SOSC_CLK.outFreq, value: 8 MHz}
235 - {id: System_clock.outFreq, value: 4 MHz}
236 settings:
237 - {id: SCGMode, value: SOSC}
238 - {id: powerMode, value: VLPR}
239 - {id: OSC32_CR_ROSCE_CFG, value: Enabled}
240 - {id: SCG.DIVCORE.scale, value: '2', locked: true}
241 - {id: SCG.DIVSLOW.scale, value: '4', locked: true}
242 - {id: SCG.FIRCDIV2.scale, value: '1'}
243 - {id: SCG.LPFLLDIV2.scale, value: '2'}
244 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
245 - {id: SCG.SCSSEL.sel, value: SCG.SOSC}
246 - {id: SCG.SIRCDIV2.scale, value: '2'}
247 - {id: SCG.SOSCDIV2.scale, value: '1'}
248 - {id: SCG.TRIMDIV.scale, value: '4'}
249 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
250 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
251 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
252 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
253 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
254 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
255 sources:
256 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
257 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
258 /* clang-format on */
259
260 /*******************************************************************************
261 * Variables for BOARD_BootClockVLPR configuration
262 ******************************************************************************/
263 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
264 {
265 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
266 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
267 .src = kSCG_SysClkSrcSysOsc, /* System OSC is selected as System Clock Source */
268 };
269 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
270 {
271 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
272 .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,/* Enable System OSC clock, Enable System OSC in low power mode */
273 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
274 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
275 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
276 };
277 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
278 {
279 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
280 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
281 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
282 };
283 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
284 {
285 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
286 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
287 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
288 .trimConfig = NULL, /* Fast IRC Trim disabled */
289 };
290 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
291 {
292 .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
293 .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
294 .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
295 .trimConfig = NULL,
296 };
297 /*******************************************************************************
298 * Code for BOARD_BootClockVLPR configuration
299 ******************************************************************************/
BOARD_BootClockVLPR(void)300 void BOARD_BootClockVLPR(void)
301 {
302 /* Init SOSC according to board configuration. */
303 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockVLPR);
304 /* Set the XTAL0 frequency based on board settings. */
305 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockVLPR.freq);
306 /* Set SCG to SOSC mode. */
307 CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
308 /* Allow SMC all power modes. */
309 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
310 /* Set VLPR power mode. */
311 SMC_SetPowerModeVlpr(SMC);
312 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
313 {
314 }
315 /* Set SystemCoreClock variable. */
316 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
317 }
318
319
