1 /*
2  * Copyright 2020 ,2021 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /***********************************************************************************************************************
9  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11  **********************************************************************************************************************/
12 /*
13  * How to setup clock using clock driver functions:
14  *
15  * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16  *    Note: The clock could not be set when it is being used as system clock.
17  *    In default out of reset, the CPU is clocked from FIRC(IRC48M),
18  *    so before setting FIRC, change to use another avaliable clock source.
19  *
20  * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21  *
22  * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23  *    Wait until the system clock source is changed to target source.
24  *
25  * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26  *    corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27  *    Supported run mode and clock restrictions could be found in Reference Manual.
28  */
29 
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v7.0
34 processor: K32L3A60xxx
35 package_id: K32L3A60VPJ1A
36 mcu_data: ksdk2_0
37 processor_version: 9.0.0
38 board: FRDM-K32L3A6
39  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
40 /* clang-format on */
41 
42 #include "fsl_msmc.h"
43 #include "clock_config.h"
44 
45 /*******************************************************************************
46  * Definitions
47  ******************************************************************************/
48 #define SCG_LPFLL_DISABLE                                 0U  /*!< LPFLL clock disabled */
49 
50 /*******************************************************************************
51  * Variables
52  ******************************************************************************/
53 /* System clock frequency. */
54 extern uint32_t SystemCoreClock;
55 
56 /*******************************************************************************
57  * Code
58  ******************************************************************************/
59 #ifndef SDK_SECONDARY_CORE
60 /*FUNCTION**********************************************************************
61  *
62  * Function Name : CLOCK_CONFIG_FircSafeConfig
63  * Description   : This function is used to safely configure FIRC clock.
64  *                 In default out of reset, the CPU is clocked from FIRC(IRC48M).
65  *                 Before setting FIRC, change to use SIRC as system clock,
66  *                 then configure FIRC.
67  * Param fircConfig  : FIRC configuration.
68  *
69  *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)70 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
71 {
72     scg_sys_clk_config_t curConfig;
73     const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
74                                              .div1 = kSCG_AsyncClkDisable,
75                                              .div2 = kSCG_AsyncClkDivBy2,
76                                              .range = kSCG_SircRangeHigh};
77     scg_sys_clk_config_t sysClkSafeConfigSource = {
78          .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
79          .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
80          .src = kSCG_SysClkSrcSirc     /* System clock source. */
81     };
82     /* Init Sirc */
83     CLOCK_InitSirc(&scgSircConfig);
84     /* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
85     CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
86     /* Wait for clock source switch finished */
87     do
88     {
89         CLOCK_GetCurSysClkConfig(&curConfig);
90     } while (curConfig.src != sysClkSafeConfigSource.src);
91 
92     /* Init Firc */
93     CLOCK_InitFirc(fircConfig);
94 }
95 #endif
96 
97 /*******************************************************************************
98  ************************ BOARD_InitBootClocks function ************************
99  ******************************************************************************/
BOARD_InitBootClocks(void)100 void BOARD_InitBootClocks(void)
101 {
102     BOARD_BootClockRUN();
103 }
104 
105 /*******************************************************************************
106  ********************** Configuration BOARD_BootClockRUN ***********************
107  ******************************************************************************/
108 /* clang-format off */
109 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
110 !!Configuration
111 name: BOARD_BootClockRUN
112 called_from_default_init: true
113 outputs:
114 - {id: Bus_clock.outFreq, value: 48 MHz}
115 - {id: Core_clock.outFreq, value: 48 MHz}
116 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
117 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
118 - {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
119 - {id: LPO_CLK.outFreq, value: 1 kHz}
120 - {id: Platform_clock.outFreq, value: 48 MHz}
121 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
122 - {id: Slow_clock.outFreq, value: 24 MHz}
123 - {id: System_clock.outFreq, value: 48 MHz}
124 settings:
125 - {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
126 - {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
127 - {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
128 - {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
129 - {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
130 - {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
131 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
132  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
133 /* clang-format on */
134 
135 /*******************************************************************************
136  * Variables for BOARD_BootClockRUN configuration
137  ******************************************************************************/
138 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
139     {
140         .divSlow = kSCG_SysClkDivBy2,             /* Slow Clock Divider: divided by 2 */
141         .divBus = kSCG_SysClkDivBy1,              /* Bus Clock Divider: divided by 1 */
142         .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
143         .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
144         .src = kSCG_SysClkSrcFirc,                /* Fast IRC is selected as System Clock Source */
145     };
146 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
147     {
148         .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
149         .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
150         .div2 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 2: Clock output is disabled */
151         .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
152         .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
153     };
154 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
155     {
156         .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
157         .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
158         .div2 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 2: divided by 1 */
159         .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
160         .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
161         .trimConfig = NULL,
162     };
163 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
164     {
165         .enableMode = SCG_LPFLL_DISABLE,          /* LPFLL clock disabled */
166         .div1 = kSCG_AsyncClkDivBy1,              /* Low Power FLL Clock Divider 1: divided by 1 */
167         .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
168         .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
169         .range = kSCG_LpFllRange48M,              /* LPFLL is trimmed to 48MHz */
170         .trimConfig = NULL,
171     };
172 /*******************************************************************************
173  * Code for BOARD_BootClockRUN configuration
174  ******************************************************************************/
BOARD_BootClockRUN(void)175 void BOARD_BootClockRUN(void)
176 {
177 #ifndef SDK_SECONDARY_CORE
178     scg_sys_clk_config_t curConfig;
179 
180     /* Init FIRC */
181     CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
182     /* Set SCG to FIRC mode. */
183     CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
184     /* Wait for clock source switch finished */
185     do
186     {
187         CLOCK_GetCurSysClkConfig(&curConfig);
188     } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
189     /* Init SIRC */
190     CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
191     /* Init LPFLL */
192     CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
193     /* Set SystemCoreClock variable. */
194     SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
195 #endif
196 }
197 
198 /*******************************************************************************
199  ********************* Configuration BOARD_BootClockHSRUN **********************
200  ******************************************************************************/
201 /* clang-format off */
202 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
203 !!Configuration
204 name: BOARD_BootClockHSRUN
205 outputs:
206 - {id: Bus_clock.outFreq, value: 72 MHz}
207 - {id: Core_clock.outFreq, value: 72 MHz}
208 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
209 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
210 - {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
211 - {id: LPFLLDIV1_CLK.outFreq, value: 72 MHz}
212 - {id: LPO_CLK.outFreq, value: 1 kHz}
213 - {id: Platform_clock.outFreq, value: 72 MHz}
214 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
215 - {id: Slow_clock.outFreq, value: 8 MHz}
216 - {id: System_clock.outFreq, value: 72 MHz}
217 settings:
218 - {id: SCGMode, value: LPFLL}
219 - {id: powerMode, value: HSRUN}
220 - {id: SCG.DIVCORE.scale, value: '1', locked: true}
221 - {id: SCG.DIVSLOW.scale, value: '9'}
222 - {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
223 - {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
224 - {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
225 - {id: SCG.LPFLLDIV1.scale, value: '1'}
226 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
227 - {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
228 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
229 - {id: SCG.TRIMDIV.scale, value: '24'}
230 - {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
231 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
232  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
233 /* clang-format on */
234 
235 /*******************************************************************************
236  * Variables for BOARD_BootClockHSRUN configuration
237  ******************************************************************************/
238 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
239     {
240         .divSlow = kSCG_SysClkDivBy9,             /* Slow Clock Divider: divided by 9 */
241         .divBus = kSCG_SysClkDivBy1,              /* Bus Clock Divider: divided by 1 */
242         .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
243         .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
244         .src = kSCG_SysClkSrcLpFll,               /* Low power FLL is selected as System Clock Source */
245     };
246 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
247     {
248         .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
249         .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
250         .div2 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 2: Clock output is disabled */
251         .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
252         .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
253     };
254 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
255     {
256         .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
257         .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
258         .div2 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 2: divided by 1 */
259         .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
260         .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
261         .trimConfig = NULL,
262     };
263 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
264     {
265         .enableMode = kSCG_LpFllEnable,           /* Enable LPFLL clock */
266         .div1 = kSCG_AsyncClkDivBy1,              /* Low Power FLL Clock Divider 1: divided by 1 */
267         .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
268         .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
269         .range = kSCG_LpFllRange72M,              /* LPFLL is trimmed to 72MHz */
270         .trimConfig = NULL,
271     };
272 /*******************************************************************************
273  * Code for BOARD_BootClockHSRUN configuration
274  ******************************************************************************/
BOARD_BootClockHSRUN(void)275 void BOARD_BootClockHSRUN(void)
276 {
277 #ifndef SDK_SECONDARY_CORE
278     scg_sys_clk_config_t curConfig;
279 
280     /* Init FIRC */
281     CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
282     /* Init LPFLL */
283     CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
284 #if defined(SDK_CORE_ID_CM4)
285     /* Set HSRUN power mode */
286     SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
287     SMC_SetPowerModeHsrun(SMC0);
288     while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
289     {
290     }
291 #elif defined(SDK_CORE_ID_CM0PLUS)
292     SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
293     SMC_SetPowerModeHsrun(SMC1);
294     while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
295     {
296     }
297 #endif
298     /* Set SCG to LPFLL mode. */
299     CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
300     /* Wait for clock source switch finished */
301     do
302     {
303         CLOCK_GetCurSysClkConfig(&curConfig);
304     } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
305     /* Init SIRC */
306     CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
307     /* Set SystemCoreClock variable. */
308     SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
309 #endif
310 }
311 
312 /*******************************************************************************
313  ********************* Configuration BOARD_BootClockVLPR ***********************
314  ******************************************************************************/
315 /* clang-format off */
316 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
317 !!Configuration
318 name: BOARD_BootClockVLPR
319 outputs:
320 - {id: Bus_clock.outFreq, value: 2 MHz}
321 - {id: Core_clock.outFreq, value: 4 MHz}
322 - {id: LPO_CLK.outFreq, value: 1 kHz}
323 - {id: Platform_clock.outFreq, value: 4 MHz}
324 - {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
325 - {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
326 - {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
327 - {id: Slow_clock.outFreq, value: 4000/9 kHz}
328 - {id: System_clock.outFreq, value: 4 MHz}
329 settings:
330 - {id: SCGMode, value: SIRC}
331 - {id: powerMode, value: VLPR}
332 - {id: SCG.DIVBUS.scale, value: '2', locked: true}
333 - {id: SCG.DIVCORE.scale, value: '2', locked: true}
334 - {id: SCG.DIVSLOW.scale, value: '9'}
335 - {id: SCG.FIRCDIV1.scale, value: '1'}
336 - {id: SCG.SCSSEL.sel, value: SCG.SIRC}
337 - {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
338 - {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
339 - {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
340  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
341 /* clang-format on */
342 
343 /*******************************************************************************
344  * Variables for BOARD_BootClockVLPR configuration
345  ******************************************************************************/
346 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
347     {
348         .divSlow = kSCG_SysClkDivBy9,             /* Slow Clock Divider: divided by 9 */
349         .divBus = kSCG_SysClkDivBy2,              /* Bus Clock Divider: divided by 2 */
350         .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
351         .divCore = kSCG_SysClkDivBy2,             /* Core Clock Divider: divided by 2 */
352         .src = kSCG_SysClkSrcSirc,                /* Slow IRC is selected as System Clock Source */
353     };
354 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
355     {
356         .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
357         .div1 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 1: divided by 1 */
358         .div2 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 2: divided by 1 */
359         .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
360         .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
361     };
362 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
363     {
364         .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
365         .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
366         .div2 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 2: Clock output is disabled */
367         .div3 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 3: Clock output is disabled */
368         .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
369         .trimConfig = NULL,
370     };
371 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
372     {
373         .enableMode = SCG_LPFLL_DISABLE,          /* LPFLL clock disabled */
374         .div1 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 1: Clock output is disabled */
375         .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
376         .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
377         .range = kSCG_LpFllRange48M,              /* LPFLL is trimmed to 48MHz */
378         .trimConfig = NULL,
379     };
380 /*******************************************************************************
381  * Code for BOARD_BootClockVLPR configuration
382  ******************************************************************************/
BOARD_BootClockVLPR(void)383 void BOARD_BootClockVLPR(void)
384 {
385 #ifndef SDK_SECONDARY_CORE
386     scg_sys_clk_config_t curConfig;
387 
388     /* Init SIRC */
389     CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
390     /* Set SCG to SIRC mode. */
391     CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
392     /* Init FIRC */
393     CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
394     /* Init LPFLL */
395     CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
396 #if defined(SDK_CORE_ID_CM4)
397     /* Set VLPR power mode. */
398     SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
399     SMC_SetPowerModeVlpr(SMC0);
400     while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
401     {
402     }
403 #elif defined(SDK_CORE_ID_CM0PLUS)
404     /* Set VLPR power mode. */
405     SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
406     SMC_SetPowerModeVlpr(SMC1);
407     while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
408     {
409     }
410 #endif
411     /* Wait for clock source switch finished */
412     do
413     {
414         CLOCK_GetCurSysClkConfig(&curConfig);
415     } while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
416     /* Set SystemCoreClock variable. */
417     SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
418 #endif
419 }
420 
421