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Searched refs:Divider (Results 1 – 19 of 19) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dsystem_MK66F18.c110 uint16_t Divider; in SystemCoreClockUpdate() local
135 Divider = 1536U; in SystemCoreClockUpdate()
138 Divider = 1280U; in SystemCoreClockUpdate()
141 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
145 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
147 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
184 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
185 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
186 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
187 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dsystem_MKL25Z4.c135 uint16_t Divider; in SystemCoreClockUpdate() local
147 Divider = 1536U; in SystemCoreClockUpdate()
150 Divider = 1280U; in SystemCoreClockUpdate()
153 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
157 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
159 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
194 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
195 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
196 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
197 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
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/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dsystem_MK22F51212.c125 uint16_t Divider; in SystemCoreClockUpdate() local
150 Divider = 1536U; in SystemCoreClockUpdate()
153 Divider = 1280U; in SystemCoreClockUpdate()
156 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
160 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
162 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
198 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
199 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
200 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
201 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
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/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dsystem_MK64F12.c129 uint16_t Divider; in SystemCoreClockUpdate() local
154 Divider = 1536U; in SystemCoreClockUpdate()
157 Divider = 1280U; in SystemCoreClockUpdate()
160 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
164 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
166 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
202 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
203 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
204 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
205 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
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/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dsystem_MK80F25615.c104 uint16_t Divider; in SystemCoreClockUpdate() local
129 Divider = 1536U; in SystemCoreClockUpdate()
132 Divider = 1280U; in SystemCoreClockUpdate()
135 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
139 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
141 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
177 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
178 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
179 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
180 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
[all …]
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dsystem_MK82F25615.c98 uint16_t Divider; in SystemCoreClockUpdate() local
123 Divider = 1536U; in SystemCoreClockUpdate()
126 Divider = 1280U; in SystemCoreClockUpdate()
129 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
133 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
135 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
171 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
172 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
173 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
174 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
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/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dsystem_MKW22D5.c144 uint16_t Divider; in SystemCoreClockUpdate() local
160 Divider = 1536U; in SystemCoreClockUpdate()
163 Divider = 1280U; in SystemCoreClockUpdate()
166 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
170 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
172 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
207 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
208 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
209 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
210 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
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/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dsystem_MKW24D5.c144 uint16_t Divider; in SystemCoreClockUpdate() local
160 Divider = 1536U; in SystemCoreClockUpdate()
163 Divider = 1280U; in SystemCoreClockUpdate()
166 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
170 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
172 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
207 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
208 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
209 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
210 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dsystem_MKV58F24.c112 uint16_t Divider; in SystemCoreClockUpdate() local
124 Divider = 1536; in SystemCoreClockUpdate()
127 Divider = 1280; in SystemCoreClockUpdate()
130 Divider = (uint16_t)(32U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
134 Divider = (uint16_t)(1U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
136 …MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FL… in SystemCoreClockUpdate()
172 Divider = (1U + (MCG->C5 & MCG_C5_PRDIV_MASK)); in SystemCoreClockUpdate()
173 …MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL refe… in SystemCoreClockUpdate()
174 Divider = ((MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
175 …MCGOUTClock = ((MCGOUTClock * Divider) >> 1U); /* Calculate the MCG outp… in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dsystem_MKV56F24.c112 uint16_t Divider; in SystemCoreClockUpdate() local
124 Divider = 1536; in SystemCoreClockUpdate()
127 Divider = 1280; in SystemCoreClockUpdate()
130 Divider = (uint16_t)(32U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
134 Divider = (uint16_t)(1U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
136 …MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FL… in SystemCoreClockUpdate()
172 Divider = (1U + (MCG->C5 & MCG_C5_PRDIV_MASK)); in SystemCoreClockUpdate()
173 …MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL refe… in SystemCoreClockUpdate()
174 Divider = ((MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
175 …MCGOUTClock = ((MCGOUTClock * Divider) >> 1U); /* Calculate the MCG outp… in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dsystem_MKW41Z4.c100 uint16_t Divider; in SystemCoreClockUpdate() local
114 Divider = 1536U; in SystemCoreClockUpdate()
117 Divider = 1280U; in SystemCoreClockUpdate()
120 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
124 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
126 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
164 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
165 …MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selecte… in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
Dsystem_MKW21Z4.c99 uint16_t Divider; in SystemCoreClockUpdate() local
113 Divider = 1536U; in SystemCoreClockUpdate()
116 Divider = 1280U; in SystemCoreClockUpdate()
119 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
123 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
125 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
163 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
164 …MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selecte… in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
Dsystem_MKW31Z4.c100 uint16_t Divider; in SystemCoreClockUpdate() local
114 Divider = 1536U; in SystemCoreClockUpdate()
117 Divider = 1280U; in SystemCoreClockUpdate()
120 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
124 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
126 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
164 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
165 …MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selecte… in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
Dsystem_MKW30Z4.c216 uint16_t Divider; in SystemCoreClockUpdate() local
230 Divider = 1536U; in SystemCoreClockUpdate()
233 Divider = 1280U; in SystemCoreClockUpdate()
236 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
240 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
242 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
280 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
281 …MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selecte… in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
Dsystem_MKW20Z4.c216 uint16_t Divider; in SystemCoreClockUpdate() local
230 Divider = 1536U; in SystemCoreClockUpdate()
233 Divider = 1280U; in SystemCoreClockUpdate()
236 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
240 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
242 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
280 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
281 …MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selecte… in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
Dsystem_MKW40Z4.c216 uint16_t Divider; in SystemCoreClockUpdate() local
230 Divider = 1536U; in SystemCoreClockUpdate()
233 Divider = 1280U; in SystemCoreClockUpdate()
236 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
240 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
242 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
280 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
281 …MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selecte… in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
Dsystem_MKE14F16.c113 uint16_t Divider, prediv, multi; in SystemCoreClockUpdate() local
114 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
144 SystemCoreClock = (SCGOUTClock / Divider); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
Dsystem_MKE16F16.c113 uint16_t Divider, prediv, multi; in SystemCoreClockUpdate() local
114 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
144 SystemCoreClock = (SCGOUTClock / Divider); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
Dsystem_MKE18F16.c113 uint16_t Divider, prediv, multi; in SystemCoreClockUpdate() local
114 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
144 SystemCoreClock = (SCGOUTClock / Divider); in SystemCoreClockUpdate()