Lines Matching refs:Divider
144 uint16_t Divider; in SystemCoreClockUpdate() local
160 Divider = 1536U; in SystemCoreClockUpdate()
163 Divider = 1280U; in SystemCoreClockUpdate()
166 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
170 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
172 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
207 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
208 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
209 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
210 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
217 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
218 …MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selecte… in SystemCoreClockUpdate()