Lines Matching refs:Divider
135 uint16_t Divider; in SystemCoreClockUpdate() local
147 Divider = 1536U; in SystemCoreClockUpdate()
150 Divider = 1280U; in SystemCoreClockUpdate()
153 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
157 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
159 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
194 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
195 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
196 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
197 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
204 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
205 …MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selecte… in SystemCoreClockUpdate()