1 /*
2 ** ###################################################################
3 ** Processors: MKV56F1M0VLL24
4 ** MKV56F1M0VLQ24
5 ** MKV56F1M0VMD24
6 ** MKV56F512VLL24
7 ** MKV56F512VLQ24
8 ** MKV56F512VMD24
9 **
10 ** Compilers: Freescale C/C++ for Embedded ARM
11 ** GNU C Compiler
12 ** IAR ANSI C/C++ Compiler for ARM
13 ** Keil ARM C/C++ Compiler
14 ** MCUXpresso Compiler
15 **
16 ** Reference manual: KV5XP144M240RM Rev. 3, 02/2016
17 ** Version: rev. 0.3, 2016-02-29
18 ** Build: b181105
19 **
20 ** Abstract:
21 ** Provides a system configuration function and a global variable that
22 ** contains the system frequency. It configures the device and initializes
23 ** the oscillator (PLL) that is part of the microcontroller device.
24 **
25 ** Copyright 2016 Freescale Semiconductor, Inc.
26 ** Copyright 2016-2018 NXP
27 ** All rights reserved.
28 **
29 ** SPDX-License-Identifier: BSD-3-Clause
30 **
31 ** http: www.nxp.com
32 ** mail: support@nxp.com
33 **
34 ** Revisions:
35 ** - rev. 0.1 (2015-02-24)
36 ** Initial version.
37 ** - rev. 0.2 (2015-10-21)
38 ** UART0 - removed LON functionality.
39 ** FMC - corrected base address.
40 ** - rev. 0.3 (2016-02-29)
41 ** PORT - removed registers GICLR, GICHR.
42 **
43 ** ###################################################################
44 */
45
46 /*!
47 * @file MKV56F24
48 * @version 0.3
49 * @date 2016-02-29
50 * @brief Device specific configuration file for MKV56F24 (implementation file)
51 *
52 * Provides a system configuration function and a global variable that contains
53 * the system frequency. It configures the device and initializes the oscillator
54 * (PLL) that is part of the microcontroller device.
55 */
56
57 #include <stdint.h>
58 #include "fsl_device_registers.h"
59
60
61
62 /* ----------------------------------------------------------------------------
63 -- Core clock
64 ---------------------------------------------------------------------------- */
65
66 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
67
68 /* ----------------------------------------------------------------------------
69 -- SystemInit()
70 ---------------------------------------------------------------------------- */
71
SystemInit(void)72 void SystemInit (void) {
73 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
74 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
75 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
76
77 /* Watchdog disable */
78
79 #if (DISABLE_WDOG)
80 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
81 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
82 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
83 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
84 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
85 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
86 WDOG_STCTRLH_WAITEN_MASK |
87 WDOG_STCTRLH_STOPEN_MASK |
88 WDOG_STCTRLH_ALLOWUPDATE_MASK |
89 WDOG_STCTRLH_CLKSRC_MASK |
90 0x0100U;
91 #endif /* (DISABLE_WDOG) */
92
93 /* Enable instruction and data caches */
94 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
95 SCB_EnableICache();
96 #endif
97 #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
98 SCB_EnableDCache();
99 #endif
100
101 SystemInitHook();
102 }
103
104 /* ----------------------------------------------------------------------------
105 -- SystemCoreClockUpdate()
106 ---------------------------------------------------------------------------- */
107
SystemCoreClockUpdate(void)108 void SystemCoreClockUpdate (void) {
109
110
111 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
112 uint16_t Divider;
113
114 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
115 /* Output of FLL or PLL is selected */
116 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0U) {
117 /* FLL is selected */
118 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0U) {
119 /* External reference clock is selected */
120 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
121 if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0U) {
122 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
123 case (uint8_t)MCG_C1_FRDIV(0x07):
124 Divider = 1536;
125 break;
126 case (uint8_t)MCG_C1_FRDIV(0x06):
127 Divider = 1280;
128 break;
129 default:
130 Divider = (uint16_t)(32U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
131 break;
132 }
133 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0U) */
134 Divider = (uint16_t)(1U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
135 }
136 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
137 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0U)) */
138 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
139 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0U)) */
140 /* Select correct multiplier to calculate the MCG output clock */
141 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
142 case 0x0u:
143 MCGOUTClock *= 640U;
144 break;
145 case 0x20u:
146 MCGOUTClock *= 1280U;
147 break;
148 case 0x40u:
149 MCGOUTClock *= 1920U;
150 break;
151 case 0x60u:
152 MCGOUTClock *= 2560U;
153 break;
154 case 0x80u:
155 MCGOUTClock *= 732U;
156 break;
157 case 0xA0u:
158 MCGOUTClock *= 1464U;
159 break;
160 case 0xC0u:
161 MCGOUTClock *= 2197U;
162 break;
163 case 0xE0u:
164 MCGOUTClock *= 2929U;
165 break;
166 default:
167 MCGOUTClock *= 640U;
168 break;
169 }
170 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0U)) */
171 /* PLL is selected */
172 Divider = (1U + (MCG->C5 & MCG_C5_PRDIV_MASK));
173 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
174 Divider = ((MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
175 MCGOUTClock = ((MCGOUTClock * Divider) >> 1U); /* Calculate the MCG output clock = VCO/2; VCO = (MCGOUTClock * Divider) */
176 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0U)) */
177 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
178 /* Internal reference clock is selected */
179 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0U) {
180 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
181 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0U)) */
182 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
183 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0U)) */
184 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
185 /* External reference clock is selected */
186 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
187 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
188 /* Reserved value */
189 return;
190 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
191 SystemCoreClock = (MCGOUTClock / (1U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
192
193 }
194
195 /* ----------------------------------------------------------------------------
196 -- SystemInitHook()
197 ---------------------------------------------------------------------------- */
198
SystemInitHook(void)199 __attribute__ ((weak)) void SystemInitHook (void) {
200 /* Void implementation of the weak function. */
201 }
202
